Tech jobs

Staff Design Verification Engineer

APACStaff

automation ethernet fpga pcie perl +3 skills

Design verification engineer building UVM testbenches for high-speed interconnects (PCIe, CXL, AXI) to ensure ASIC/subsystem correctness before tape-out.

Infrastructure Design Verification Staff Engineer

APACStaff

Designs and verifies hardware infrastructure, focusing on DDR subsystem verification for Qualcomm’s next-gen products. Uses UVM, SystemVerilog, and debug tools to create test plans, integrate verification IP, and ensure high-quality verification of digital/analog/RF systems.

fpga verilog

cpp embedded-systems fpga python quantization +2 skills

Video Codec Design Engineer

APAC

Taiwan

Video Codec Design Engineer, up to Staff Location: Taipei, Taipei City, Taiwan Department: ASICS Engineering Work Location: onsite Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group…

CPU Physical Design Engineer

APAC

cpp fpga perl python tcl +1 skills

Designs and optimizes CPU physical layouts using Place & Route tools (FC/Innovus), STA (Primetime/Tempus), and UPF/CPF for low-power, high-speed ASICs.

scalian

Siemens Digital Industries Software

Avionics Hardware Engineer

Open 19d Europe

Italy

Design and verify FPGA/electronic hardware for avionics systems using VHDL/Verilog, schematics, and lab testing; collaborate on safety-critical projects.

fpga verilog vhdl

Open 19d RemoteEurope, WorldwideSenior

Senior Software Engineer C/C++

Poland

Senior C/C++ engineer building Electronic Design Automation tools that help global manufacturers design chips and systems faster and more cost-effectively.

automation bash cpp java verilog +2 skills

207 200 – 356 500 PLN

Google

automation cpp ethernet express fpga +7 skills

Emulation Hardware Engineer, Google Cloud

Open 19d MENA

Israel

Develop and maintain emulation models and infrastructure for Google’s custom silicon, scripting automation and debugging hardware flows to accelerate product development.

Infineon Technologies

altium cad fpga kicad verilog +1 skills

Digital Design/FPGA Engineer

Open 38d EuropeContract

Ukraine

Designs and debugs FPGA prototypes by converting ASIC RTL to FPGA, writes test benches, and develops hardware companion boards.

Microsoft

Open 19d On-siteAPACFull-timeSenior

Senior Design Verification Engineer

azure cloud cpp ethernet pcie +4 skills

Design verification engineer building and debugging SystemVerilog/UVM testbenches for custom AI silicon IP and SoCs, ensuring functionally correct RTL before tape-out.

Jane Street

Hardware Engineer (FPGA/ASIC)

Open 29d North America

fpga networking ocaml verilog vhdl

About the Position We are looking to hire engineers with experience in both software and hardware design to help us build our FPGA or ASIC-based applications. We're big believers in the ability of tools to make…

TalentMinted

Open 20d EuropePart-timeSenior

Senior FPGA / Radar Systems Engineer — Berlin, Germany

Germany

Senior FPGA engineer building real-time radar, GPR and SAR systems in Berlin, integrating high-speed ADCs, RF frontends and embedded Linux on Xilinx/AMD platforms.

cpp data-pipelines embedded-linux embedded-software ethernet +7 skills

70 000 – 120 000 €

Solidigm

cordova fpga pcie smartrecruiters verilog

SSD Tester Development Engineer

APAC

China

Designs and maintains NVMe SSD test systems, including PCIe circuits, FPGA firmware, and signal integrity for next-gen storage hardware.

Intel

IP RTL Design Engineer

APACFull-time

firewall observability verilog

Designs and implements RTL logic for Intel’s IP blocks, focusing on secure memory access, error handling, and debug/telemetry features to ensure high-performance SoC reliability.

Intel

HybridNorth AmericaFull-timeMiddle

Software Engineer, Silicon CAD Tool Development

ai analytics automation cad ci-cd +12 skills

Develops a new automation tool for silicon CAD (chassis automation) to generate RTL, register definitions, and verification collateral from user requirements, collaborating with RTL, verification, and SoC teams using Python, structured schemas, and CI/CD pipelines.

149 600 – 211 200 $

ChipAgents

Open 17d On-siteNorth America

Design and Verification Engineer

agentic-ai ai cloud design-patterns machine-learning +2 skills

Design and verify RTL hardware designs and SystemVerilog/UVM testbenches to train AI agents that automate chip design workflows.

150 000 – 350 000 $

Rambus

Open 19d North AmericaFull-timePrincipal H-1B sponsor history

Design Verification Principal Engineer

Principal Engineer designs and runs pre-silicon verification for DDR, HBM, and GDDR memory controller IP using SystemVerilog and UVM, with coverage-driven test suites and regression monitoring.

ai python tcl verilog

127 400 – 236 600 $

Rambus

Open 19d EuropeFull-timeLead H-1B sponsor history

Lead MTS Design Verification Engineer - PCIe Controller products

Bulgaria

Lead verification engineer building testbenches and coverage plans for PCIe/CXL controller IP using SystemVerilog/UVM and scripting in Python/TCL.

ai express pcie python systemverilog +2 skills

Rambus

Open 19d North AmericaFull-timePrincipal H-1B sponsor history

Principal PCIe Logic Design

ai pcie prototyping verilog

Principal PCIe logic engineer designs next-gen PCIe IP in SystemVerilog, collaborates with verification teams, and prototypes on FPGAs.

108 300 – 201 100 $

Western Digital