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TechTriad
3 weeks ago

Full Stack Engineer - AWS/React

Open 20d HybridNorth AmericaContract
United States

Build and deploy serverless AWS apps with React frontends, using Lambda, API Gateway, Cognito, and DynamoDB for rapid prototyping in a 6-month contract role.

ai analytics angular api authentication +17 skills
115 000 – 185 000 $
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Bosch
3 weeks ago

System Architect

Europe
France

Designs and optimizes complex System-on-Chip architectures for automotive electronics, balancing hardware/software partitions and ensuring compliance with ISO 26262 and ISO 21434 safety/security standards.

ethernet matlab pcie python sysml +2 skills
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Astera Labs
3 weeks ago

Junior Design Verification Engineer

Open 72d MENAJunior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Junior engineer builds and runs test environments to verify next-gen AI connectivity chips using SystemVerilog/UVM and debugs hardware issues with design teams.

ai cpp ethernet pcie python +3 skills
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Cisco
3 weeks ago

FPGA Design Engineer

Open 20d APAC
India

Designs and validates FPGA logic for networking hardware using Verilog/VHDL, vendor tools (Vivado/Quartus), and industry-standard flows to ensure first-pass success.

ai cisco ethernet fpga pcie +5 skills
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Intel
3 weeks ago

Senior ATE Test Engineer

Open 19d HybridMENASenior
Israel

Define and implement automated test equipment (ATE) strategies for next-gen AI hardware, optimizing yield and test costs while collaborating with design and manufacturing teams.

agile ai pcie perl python
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AMD
3 weeks ago

High Speed IO Analog Mixed Signal Design Engineer

Open 21d North America
United States

Designs high-speed analog/mixed-signal I/O circuits (SerDes, memory PHYs, chip-to-chip links) for next-gen AMD processors using advanced FinFET nodes and Cadence tools.

ai cloud go-to-market ios pcie
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Analog Devices: Mixed-signal and digital signal processing ICs
3 weeks ago

Staff Digital Design Engineer

HybridMENA, North AmericaFull-timeStaff

Staff Engineer, Digital Design Engineering Location: US, MA, Chelmsford, Elizabeth Time Type: Full time Job Description About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that…

ai automation business-development cpp csharp +7 skills
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Weekday
3 weeks ago

SOC Architect

APACFull-time
India

SOC Architect Team: Technology, Information and Media Location: Bengaluru Commitment: Full-time Workplace Type: onsite Salary: We are looking for an experienced and highly motivated Lead SoC Architect to lead the…

ai cpp ethernet fpga linux +3 skills
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Cadence Backed by Y Combinator
3 weeks ago

Sr Principal Design Engineer

Open 22d APACPrincipal
China

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Joining our Palladium and Protium solution team, work with a group of advanced interface and memory protocol…

ai automation cpp ethernet linux +6 skills
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Microsoft
3 weeks ago

Principal Subsystem Engineer (Design or DV)

Open 22d On-siteNorth AmericaInternshipPrincipal
United States

Leads hardware subsystem design or verification for Microsoft’s AI SoC (Artificial Intelligence System on Chip) to optimize cloud infrastructure, focusing on high-performance IP, SoC design, and debugging across RTL, synthesis, and post-silicon stages.

agile ai azure cloud cpp +5 skills
188 000 – 304 200 $
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Astera Labs
3 weeks ago

Executive Sales Representative

Open 72d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Taiwan

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…

ai cloud ethernet networking pcie
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Astera Labs
3 weeks ago

Expert IC Package Design Lead

Open 72d MENALead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Leads the design and development of advanced semiconductor package architectures for high-performance AI connectivity chips, collaborating with cross-functional teams to optimize electrical, thermal, and mechanical performance from concept to production.

ai cloud ethernet networking pcie
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Astera Labs
3 weeks ago

Hardware Design Engineering, Director - AEC / SCM & China Customer Support - Shanghai

Open 72d APACContract H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
China

Leads a Shanghai hardware design team to develop high-speed Active Electrical Cables and Smart Cable Modules for AI infrastructure, while providing local customer engineering support to China-based hyperscalers and OEMs.

ai ansys assembly backbone bash +8 skills
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Astera Labs
3 weeks ago

Hardware Design Engineering, Director - OEM, Silicon Validation Platforms & Rack-Scale Design - Taiwan

Open 72d APACContract H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Taiwan

Lead a new Taiwan hardware engineering hub to design validation platforms and rack-scale systems for AI connectivity, while partnering with OEMs across Asia to integrate Astera Labs’ silicon into their products.

ai airflow ansys aws cloud +3 skills
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Astera Labs
3 weeks ago

Hardware Lab Engineer

Open 72d North America H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Hardware Lab Engineer at Astera Labs in San Jose sets up and maintains test environments for silicon validation of AI connectivity solutions like PCIe, CXL, and Ethernet, using high-speed test equipment and Python automation.

ai automation ethernet jtag linux +4 skills
160 000 – 200 000 $
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Astera Labs
3 weeks ago

Manager, Physical Design Engineer

Open 72d On-siteNorth America H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Manages a team of physical design engineers in Toronto to implement high-speed connectivity ASICs for AI infrastructure, using advanced EDA tools and TSMC nodes.

agentic-ai ai automation cad ethernet +4 skills
180 000 – 220 000 CAD
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Astera Labs
3 weeks ago

Senior/ Staff Physical Design Engineer

Open 72d MENAStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs and implements high-performance semiconductor chips for AI infrastructure, focusing on physical design flows, signoff, and automation in advanced process nodes.

ai automation ethernet pcie python +1 skills
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Astera Labs
3 weeks ago

Principal Design Verification Engineer

Open 72d North AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Design Verification Engineer at Astera Labs designs and verifies advanced ASICs for AI infrastructure using SystemVerilog, UVM, and scripting languages, ensuring robust connectivity solutions for server and networking applications.

ai cpp ethernet networking pcie +3 skills
185 000 – 230 000 $
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Astera Labs
3 weeks ago

Principal Digital Design Engineer

Open 72d North AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Digital Design Engineer at Astera Labs designing high-performance AI connectivity silicon, owning RTL implementation through silicon bring-up for PCIe, CXL, and other protocols.

ai automation cad ethernet networking +1 skills
185 000 – 230 000 $
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Astera Labs
3 weeks ago

Principal Digital Design Engineer (AI Fabric)

Open 72d North AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.

ai automation cad ethernet networking +1 skills
185 000 – 230 000 $
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