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ASIC Design Engineer
Design next-gen Ethernet ASICs for AI/HPC networks, writing micro-arch specs, closing timing, and verifying RTL blocks to optimize silicon performance.
Staff Hardware Digital Engineer
Designs next-gen high-speed mixed-signal test instruments for EV, ADAS, aerospace, and semiconductors, including FPGA/CPLD development, validation, and system-level debugging.
Staff Hardware Digital Engineer
Designs high-speed mixed-signal test instruments and FPGA/CPLD logic for NI’s modular PXI systems used in EV, ADAS, aerospace, semiconductors, and electronics.
Senior Architect, NVLink
Senior Architect defines next-gen chip interconnects like NVLink, optimizing performance and power while driving ASIC design and cross-team implementation.
Senior FPGA Engineer (VHDL/Verilog)
Designs and optimizes VHDL/Verilog hardware components for networking systems (SmartNICs, optical switches), writes test cases in Python, performs timing analysis, and collaborates with software/networking teams on system-level debugging.
Digital IC Design Engineer - USB Products
Designs and verifies high-speed USB 2.0 and eUSB2 chips, writing RTL code and debugging mixed-signal circuits for next-gen AI and IoT solutions.
Engineer Embedded Software
Develop and test embedded cryptographic software for real-time systems in C/C++ and Rust, integrating firmware and hardware in an Agile environment with DoD Secret clearance.
Principal Logic Design Engineer
Principal Logic Design Engineer Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our…
SoC Design Verification Engineer
Design and verify next-gen System-on-Chip (SoC) components using Verilog/SystemVerilog, UVM, and C/C++ to ensure high-quality, industry-leading processor performance.
Design Verification Engineer
Design Verification Engineer at AMD builds and maintains tests to verify complex processor IP, debug failures, and collaborate with RTL and firmware teams to ensure high-quality silicon designs.
CPU Core Design Verification Engineer
Verify next-gen x86 CPU cores by writing C++/SystemVerilog tests and checkers, debug RTL issues, and drive coverage closure in a hybrid Austin office.
Digital Design Verification Engineer
Designs and enhances SystemVerilog/UVM testbenches to verify PCIe subsystem features, collaborating with architects and engineers to ensure robust RTL designs and memory subsystem performance.
Senior Design for Test Engineer
Designs and validates test solutions for digital, analog, and photonic logic in AI-focused chip platforms, using DFT methodologies like ATPG and boundary scan to ensure silicon bring-up and product readiness.
Senior Principal Digital Designer
Sr. Principal Digital Designer Location: Bangalore Time Type: Full time Job Description Role Summary We are seeking a Sr. Principal Digital Designer to lead the architecture, implementation, and integration of digital…
Senior Principal Embedded Systems Security Architect
Sr. Principal Embedded Systems Security Architect Location: Shanghai (Pudong) Time Type: Full time Job Description Shape the Security of Tomorrow's Connected World At NXP, security is at the heart of everything we…
Hardware Engineer Intern, FPGA
2027 Internship- Hardware Engineer (FPGA) Location: Austin, TX Department: Internships Virtu is an industry-leading financial technology firm that operates both proprietary trading and client-facing businesses in the…
FPGA Design Engineer
Designs and validates FPGA logic for networking hardware using Verilog/VHDL, vendor tools (Vivado/Quartus), and industry-standard flows to ensure first-pass success.