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Designs power delivery systems and PCB layouts for ASIC-based AI connectivity hardware, using Cadence OrCAD/Allegro and collaborating with cross-functional teams.
Principal Product Manager at Astera Labs in San Jose defines and drives the Smart Cable Modules product line, collaborating with hyperscalers to deliver high-bandwidth connectivity solutions for AI and cloud infrastructure using PCIe, Ethernet, CXL, and related technologies.
Principal Test Engineer at Astera Labs designs and implements automated test solutions for high-speed mixed-signal silicon SoC products, using protocols like PCIe, Ethernet, and DDR, and oversees production ramp.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Senior Data Science Engineer at Astera Labs in Haifa designs and deploys data pipelines, analyzes high-speed interface performance, and builds predictive models using Python, ML frameworks, and visualization tools to optimize AI infrastructure.
Senior software engineer building diagnostics and manufacturing tools for high-speed datacenter hardware, using Python and embedded/Linux systems to validate and bring up AI connectivity boards.
Develops and debugs firmware for Ethernet retimers in AI infrastructure, troubleshooting link failures and integrating new products from silicon bringup to deployment.
Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.
Designs and implements top-level physical design for AI-focused semiconductor chips, collaborating with cross-functional teams to meet strict performance, power, and area targets.
Designs and automates chip design flows for semiconductor connectivity solutions, using Python, Tcl, and EDA tools to optimize RTL generation and hardware development.
Designs and implements advanced semiconductor packages for high-performance AI connectivity chips, collaborating with teams to optimize electrical, thermal, and mechanical performance from concept to production.
Senior/Staff STA Engineer at Astera Labs in Israel designs and signs off timing for high-performance AI connectivity chips, using EDA tools and SDC constraints to meet aggressive data-center targets.
Leads the full lifecycle of ASIC chip development for AI infrastructure, coordinating cross-functional teams to design, fabricate, and validate semiconductor solutions.
Designs power integrity and electromigration checks for AI-focused semiconductor chips, using tools like Ansys RedHawk and Cadence Voltus to ensure reliability in advanced FinFET nodes.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Designs and automates semiconductor chip implementation flows, focusing on parasitic extraction and GenAI-driven methodologies to optimize high-speed AI connectivity chips from RTL to GDSII.
Designs power integrity and electromigration solutions for high-performance AI chips, ensuring voltage stability and reliability in advanced semiconductor nodes.
Leads engineering operations and ASIC tapeout management for a semiconductor company, driving decision velocity and execution rigor in San Jose, CA.
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