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Senior CPU Physical Design Engineer
Job Details: Job Description: The Role and Impact As a Senior CPU Physical Design Engineer , you will play a critical role in delivering Intel's next-generation high-performance CPUs from concept through…
FPGA Silicon Design Engineer
Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full…
Design Verification Engineer
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Software Engineer II, Synthesis
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the…
Lead Design Engineer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We offer amazing opportunities to grow, no matter where you are in your career. At Cadence, we hire and…
Software Engineer II (C++)
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software…
Principal Design Engineer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities Responsible for scheduling, designing, developing, and supporting IP models of system…
Design For Test Engineer III (IC)
Position: Design For Test Engineer III (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys…
Software Engineer II, Synthesis
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the…
Silicon Design Infrastructure - IP Management Solution
Designs and deploys a silicon IP management platform for AMD's chip design teams, automating workflows with EDA tools and scripting to improve performance, cost, and power efficiency in GPUs, CPUs, and APUs.
FPGA Digital Design Engineering Intern (January 2027) (4-16 months)
At Kepler Communications , we're not just imagining the future of on-demand space connectivity - we're leading it! Our mission is to provide real-time on-orbit connectivity for critical missions, enabling a new…
Principal Engineer - Design Verification
Principal Engineer responsible for verifying complex microcontroller and microprocessor designs using UVM, SystemVerilog, and EDA tools to ensure correct, safe, and secure SoC functionality.
TPU RTL Design Engineer
Designs and verifies custom TPU silicon for AI/ML acceleration, focusing on clock control, RTL implementation, and integration with Google's infrastructure.
Product Application Engineer - FPGA/Emulation & ACAP Compilation Tools
Develops and supports FPGA/emulation and ACAP compilation tools for AMD's hardware platforms, collaborating with R&D and customers to improve emulation flows and prototyping methodologies.
Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects
Designs and verifies high-performance RTL for Google's TPU inter-chip interconnects, focusing on ASIC/SoC hardware for AI and networking accelerators in data centers.
Senior Physical Design Engineer
Senior Physical Design Engineer at Bitdeer in Singapore designs and implements high-speed PCIe IP for AI chips, owning the full physical design flow from netlist to GDSII using advanced EDA tools.
Senior/Staff Front-End Engineer (IP Integration)
Develops and integrates PCIe IP blocks using Verilog RTL for a Bitcoin mining and AI cloud company, ensuring functional coverage and collaborating with verification and software teams.
Senior/Staff Front-End Design Engineer (RTL Design - RiscV)
Designs and integrates RISC-V CPU cores with custom extensions for ASIC chips in Bitcoin mining and AI cloud hardware, using Verilog/SystemVerilog and collaborating with cross-functional teams.