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HPR (Hyannis Port Research)
3 weeks ago

FPGA Engineering Intern - Summer 2027

Open 21d North AmericaInternshipIntern
United States

Build FPGA-based ultra-low-latency trading systems in Verilog/VHDL, automate RTL generation, and collaborate on real-time capital-markets infrastructure.

embedded-systems fpga linux perl python +3 skills
42 – 42 $ / hr
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RTX
3 weeks ago

Senior Hardware-in-the-Loop Electrical Engineer

Open 15d On-siteNorth AmericaFull-timeSenior
United States

Sr HWIL Electrical Engineer Location: US-AZ-TUCSON-805 ~ 1151 E Hermans Rd ~ BLDG 805 Time Type: Full time Job Description Date Posted: 2026-07-27 Country: United States of America Location: US-AZ-TUCSON-805 ~ 1151 E…

altium embedded-systems fpga technical-writing verilog +1 skills
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RTX
3 weeks ago

Hardware-in-the-Loop Electrical Engineer

Open 15d On-siteNorth AmericaFull-time
United States

HWIL Electrical Engineer II Location: US-AZ-TUCSON-805 ~ 1151 E Hermans Rd ~ BLDG 805 Time Type: Full time Job Description Date Posted: 2026-07-27 Country: United States of America Location: US-AZ-TUCSON-805 ~ 1151 E…

fpga verilog vhdl
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RTX
3 weeks ago

Senior Principal Real-time Software Engineer

Open 15d On-siteNorth AmericaFull-timePrincipal
United States

Sr Principal Real-time Software Engineer Location: US-CO-AURORA-S76 ~ 16430 E Hughes Dr ~ BLDG S76 Time Type: Full time Job Description Date Posted: 2026-08-04 Country: United States of America Location:…

agile assembly cpp embedded-software fpga +5 skills
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NVIDIA
3 weeks ago

SOC Clocks RTL Design Engineer

Open 22d MENA
Israel

Design and implement the clocking logic for NVIDIA’s next-gen networking chips, writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, and domain-crossing infrastructure.

assembly automation backbone cad networking +2 skills
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NVIDIA
3 weeks ago

Senior SOC Clocks RTL Design Engineer

Open 22d MENASenior
Israel

Lead the RTL design and implementation of clocking logic for NVIDIA’s next-gen networking chips, including PLL integration, clock distribution, and reset synchronization, guiding the team from spec to silicon.

assembly automation backbone cad networking +2 skills
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onsemi
3 weeks ago

Senior Design Verification Engineer

Open 22d APACSenior
India

Leads digital IC verification for mixed-signal IP (DACs, ADCs, PLLs) in automotive/industrial/medical products, designing SystemVerilog/UVM environments, debugging RTL, and improving verification methodologies.

embedded-software python signal-processing tcl verilog
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Microsoft
3 weeks ago

Principal Subsystem Engineer (Design or DV)

Open 22d On-siteNorth AmericaInternshipPrincipal
United States

Leads hardware subsystem design or verification for Microsoft’s AI SoC (Artificial Intelligence System on Chip) to optimize cloud infrastructure, focusing on high-performance IP, SoC design, and debugging across RTL, synthesis, and post-silicon stages.

agile ai azure cloud cpp +5 skills
188 000 – 304 200 $
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Apple
3 weeks ago

C - Focused Design Verification Engineer

Open 22d North America
United States

Designs and implements C-based tests for wireless SoC verification and power analysis, collaborating across chip disciplines to ensure functional silicon for Apple products.

assembly cpp python systemverilog verilog
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SK Hynix Memory Solution
3 weeks ago

Sr./Staff /Sr. Staff Engineer, IP Design (ASIC)

Open 71d North AmericaStaff
United States

Designs and verifies high-speed interface IP for next-gen storage subsystems (NVMe/Chiplet) in ASICs, leading RTL development through silicon bring-up for enterprise and AI data center storage solutions.

ai cloud machine-learning perl python +2 skills
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Astera Labs
3 weeks ago

Principal Physical Design Engineer, STA

Open 72d On-siteNorth AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.

ai automation cloud ethernet networking +6 skills
209 000 – 250 000 $
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Astera Labs
3 weeks ago

Senior ASIC Design Engineer

Open 72d MENASenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.

ai automation ethernet pcie perl +3 skills
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Astera Labs
3 weeks ago

Senior/ Staff Front-End CAD Engineer

Open 72d MENAStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs and automates chip design flows for semiconductor connectivity solutions, using Python, Tcl, and EDA tools to optimize RTL generation and hardware development.

ai automation backbone cad ethernet +8 skills
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Astera Labs
3 weeks ago

Design Verification Engineer (Intern 2026)

Open 71d North AmericaInternshipIntern H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Design Verification Intern at Astera Labs working on silicon engineering for high-performance compute and networking standards using RTL design languages like Verilog and SystemVerilog.

ai analytics cpp ethernet jtag +5 skills
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Astera Labs
3 weeks ago

IP Design Director

Open 55d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.

ai authentication ci-cd ethernet pcie +4 skills
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Astera Labs
3 weeks ago

SoC Design Director

Open 55d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.

ai authentication ci-cd ethernet pcie +4 skills
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Astera Labs
3 weeks ago

Staff / Principal ASIC Design Engineer

Open 38d MENAPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.

ai automation ethernet pcie perl +3 skills
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Google
3 weeks ago

Systems Design Engineer, Digital Signal Processing

North America
United States

Systems Design Engineer, Digital Signal Processing _corporate_fare_ Google _place_ Sunnyvale, CA, USA Advanced Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders;…

signal-processing systemverilog verilog
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Cadence Design Systems
3 weeks ago

Lead Software Engineer

Open 15d APACFull-timeLead
China

Lead Software Engineer - Liberate Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The candidates…

cpp linux tcl unix verilog +1 skills
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Cadence Design Systems
3 weeks ago

Principal Design Engineer

Open 15d North AmericaFull-timePrincipal
United States

Sr Principal Design Engineer Location: SAN JOSE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our North America…

cpp fpga pcie prototyping systemverilog +1 skills
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