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Leads the design and implementation of high-performance digital circuits for AI connectivity chips, using PCIe, CXL, Ethernet, and DDR protocols, from architecture to silicon bring-up.
Design Verification Intern at Astera Labs working on silicon engineering for high-performance compute and networking standards using RTL design languages like Verilog and SystemVerilog.
Develops firmware and microcontroller subsystems for AI connectivity hardware using C/C++, Python, and RTOS, debugging with JTAG and lab tools in Vancouver.
Leads a team in Hyderabad to design and implement high-speed connectivity ASICs for AI infrastructure, using advanced EDA tools and flows for full-chip physical design and tapeout.
Leads a team to verify complex semiconductor designs for AI infrastructure, focusing on PCIe, CXL, and UVM methodologies to ensure silicon success.
Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.
Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.
Leads a team to design test strategies for high-speed PCIe switch chips using advanced 2.5D/3D packaging, ensuring manufacturability and quality for AI infrastructure components.
Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.
Senior Capacity Planning Analyst at Astera Labs in San Jose builds and maintains data-driven capacity models for semiconductor supply chains, using tools like Power BI, Databricks, and Oracle to forecast production and resolve bottlenecks.
Senior Sourcing Specialist in Taipei manages procurement, supplier relations, and purchasing for Astera Labs' Asia operations, including lab equipment, facilities, and office needs across multiple cities.
Lead a team to design, build, and maintain enterprise and cloud networks using routing, switching, firewalls, and cloud connectivity for a company delivering AI infrastructure solutions.
Principal Physical Design Engineer defines and maintains reusable RTL-to-GDSII flows and automation for SoC tapeouts, integrating Cadence and Synopsys tools to optimize PPA and schedule predictability.
Leads a team to design and tape out advanced multi-die switching chips for AI infrastructure using UCIe, UALink, and PCIe Gen 6/7 in 7nm or smaller process nodes.
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