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DRAM Design Working Student in Munich (m/f/d)
Working student role in DRAM design, assisting engineers with IC schematics, simulations, and verification for high-performance memory solutions in Munich.
Senior ASIC Design Engineer
Design and verify ASICs for HP printers, leading RTL coding, verification, and silicon validation while collaborating with cross-functional teams to deliver embedded solutions.
Senior ASIC Design Engineer
Design and verify ASICs for HP printers, leading RTL coding, verification, and silicon validation while collaborating with cross-functional teams to deliver embedded solutions.
Full-Chip Senior Principal Physical Design Engineer
Lead the physical design and implementation of high-performance processor chips from RTL to GDS in advanced nodes (5nm–2nm), managing global teams and sign-offs for timing, power, and DFM.
Full-Chip Principal Physical Design Engineer
Lead the physical design and methodology for next-gen high-performance processor chips, managing RTL-to-GDS flows, timing, power, and sign-offs in advanced nodes (5nm–2nm) for server, 5G/6G, and networking applications.
Software Engineer II: Jasper R&D
Builds and tests Jasper, a formal-verification tool for clock-domain-crossing issues in chip design, using C++ and Unix workflows.
Lead Software Engineer: Jasper R&D
Lead a team enhancing Jasper, a formal verification tool for clock domain crossing in hardware design, using C++ and Unix in a fast-paced R&D environment.
ASIC/SoC Design & Verification Engineer
Design and verify ASIC/SoC hardware in Verilog/SystemVerilog, then evaluate and improve how AI models understand chip engineering tasks.
Senior FPGA Engineer
Designs and implements FPGA-based solutions for semiconductor test instruments, focusing on high-speed interfaces, memory subsystems, and signal processing using AMD/Xilinx or Intel/Altera tools.
Principal Analog Hardware Engineer
Principal Analog Hardware Engineer designs and validates high-performance analog and mixed-signal circuits for next-generation test and measurement products in Santa Rosa, CA.
Principal Analog Hardware Engineer
Principal Analog Hardware Engineer designs and validates high-performance analog and mixed-signal circuits for next-generation test and measurement products in Santa Rosa, CA.
Senior PCIe Design Engineer
Designs and integrates PCIe, CXL, and other I/O subsystems for ARM-based SoCs, writing RTL, debugging, and collaborating with verification and backend teams.
Staff PCIe Design Engineer
Designs and integrates PCIe, CXL, and other I/O subsystems for ARM-based SoCs, writing RTL, debugging, and collaborating with verification and backend teams.
FPGA Digital Engineer - 2
Design and verify FPGA modules for advanced systems, collaborating with hardware and software teams using VHDL/Verilog and Xilinx tools.
Principal FPGA Digital Engineer - 3
Principal FPGA engineer designing and verifying VHDL/Verilog modules for high-reliability electro-optical systems, using Xilinx tools and OSVVM/UVM testbenches.
FPGA Design Engineer Level 2
Designs and implements FPGA-based digital logic for space systems like satellite command and control, using VHDL/Verilog and AMD/Microchip tools.
Senior FPGA and Firmware Design Engineer
Design and implement FPGA logic in VHDL/Verilog, write embedded Linux firmware with Yocto/PetaLinux, and integrate hardware/software for aerospace and defense systems.
Hardware Engineer – Host Processor Systems
Staff Hardware Engineer – Host Processor Systems Tektronix , an operating company of Ralliant , is a place where people are challenged to explore the boundaries of what’s possible—bringing the digital future one step…
FPGA Prototype 엔지니어 (SoC/IP Prototyping)
Design and prototype next-gen AI hardware using FPGAs, focusing on SoC emulation, high-speed interfaces like PCIe/LPDDR, and bring-up for analog compute-in-memory chips.