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Integrated Circuit Design Verification Engineer
Design and verify integrated circuits for AR display systems, building UVM-based testbenches and using Siemens Questa for simulation and debug.
Hardware Development Engineer
Design and develop high-performance embedded GPS receivers for aviation, managing circuit cards and FPGAs from concept to production while ensuring aviation-grade reliability.
Lead Software Engineer: Jasper R&D
Lead a team of engineers to design and ship complex C++ features for Jasper, Cadence’s formal verification platform, while mentoring junior developers.
Senior Design Engineer
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Principal IC Digital Design - SoC Design/Micro-architecture
Principal IC Digital Design Engineer leads SoC micro-architecture, RTL development, and HW/SW co-design for advanced semiconductor solutions used in AI, cloud, and telecom.
Senior FPGA Designer
Designs and implements FPGA logic for optical telecommunication products, collaborating with hardware and firmware teams to validate and optimize high-speed data transmission systems using Verilog/SystemVerilog and AMD/Xilinx or Altera tools.
Lead Software Engineer - Liberate
Lead a team building EDA software in C/C++/TCL on Linux, focusing on semiconductor device simulation and analysis flows like SPICE, timing, and power.
Sr/ IC Design Engineer (Design Verification)
Design verification engineer building UVM-SV testbenches and coverage plans to validate complex ICs and SoCs before tape-out.
ASIC Engineer || RTL Design, Verilog, System Verilog || CDC, Lint || Exp - 4 to 7 years
Designs and validates high-performance ASIC chips for Cisco's networking solutions using Verilog/SystemVerilog, CDC, lint, and formal verification, from architecture through tape-out and lab validation.
Amazon Chip Design Engineer, Graviton Chip Design Team
Design and implement hardware components for AWS Graviton processors using Verilog, collaborating across teams to define architecture and ensure chip reliability for cloud workloads.
Senior Software Engineer, SOC Design Methodology
Senior engineer building automation tools and methodologies to accelerate NVIDIA’s ASIC and SoC chip design flows, working with EDA vendors and RTL teams.
Principal Design Validation Product Engineer, DEG
Lead validation of next-gen DRAM memory chips, defining specs, running circuit simulations, and debugging failures to ensure product quality from design through manufacturing.
Manager, SOC Verification
Sr. Manager - SOC Verification Location: India - Bangalore Time Type: Full time Job Description Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on…
Electrical Engineer, ASIC/FPGA
Electrical Engineer II- ASIC/FPGA (Onsite) Location: US-MD-ABERDEEN-APG ~ 6260 Guardian Gtwy ~ APG Time Type: Full time Job Description Date Posted: 2026-07-24 Country: United States of America Location:…
FPGA Designer
FPGA Designer Location: Modi'in (IL) Experience Level: Experienced Description Power the Future with us! At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees,…
Cybersecurity System and Requirements Engineer
Cybersecurity System and Requirements Engineer Location: Monterrey, Mexico Time Type: Full time Job Description CYBERSECURITY SYSTEM AND REQUIREMENTS ENGINEER The Cybersecurity System and Requirements Engineer is…
Principal Design Engineer
Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities…