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Silicon Design Engineer
Design and verify ASIC and semiconductor components for AMD’s next-gen processors, using Verilog/VHDL, EDA tools, and Unix/Linux workflows.
Sr. Silicon Design Engineer
Design and verify next-gen semiconductor components for AMD’s processors, focusing on ASIC, GPU, and SOC architecture using Verilog/VHDL, RTL, and EDA tools.
PMTS Software Development Engineer
Develop and optimize low-level GPU kernels to accelerate ML model training and inference, using parallel computing and quantization techniques while collaborating with researchers and engineers.
Sr. Silicon Design Engineer
Design and verify next-gen semiconductor components and ASICs using Verilog/VHDL, CMOS, and EDA tools in a Linux environment.
PMTS Silicon Design Engineer
Designs and codes processor-core RTL, collaborates on microarchitecture, and drives synthesis, timing, and power optimization for next-gen CPUs at AMD.
SMTS Silicon Design Engineer
Design and verify next-gen semiconductor chips, focusing on ASIC architecture, logic design, and physical implementation using TCL/Python scripting and timing analysis tools.
Physical Design Methodology Engineer, AI HW IP
Build and own RTL-to-GDSII flows for AI accelerators and CPUs, automating PPA exploration and signoff to speed IP delivery across nodes and variants.
Physical Design Engineer, AI Accelerator IP
Owns end-to-end physical design of AI accelerator IP blocks, from synthesis to GDSII signoff, ensuring PPA targets and customer timelines are met.
ASIC Design Engineers to our R&D site in Stockholm
Design and verify ASIC hardware modules for Axis’s ARTPEC SoC chips, using HDLs and EDA tools to accelerate surveillance-camera functions in a collaborative R&D team.
Firmware Engineer
Design and develop VHDL-based FPGA firmware for high-reliability embedded systems in the defence sector, collaborating with hardware and software teams.
ASIC Physical Design Engineer - 7 to 10 years - Pune
Design and implement advanced ASIC/SoC physical design flows for Cisco’s silicon photonics driver ICs, focusing on 100G–400G optical interconnects using tools like Cadence Innovus, Tempus, and Calibre.
Electronic Hardware Design Engineer
Designs and develops high-performance PCB and system architectures for AI/HPC networking hardware, collaborating with cross-functional teams to bring up and qualify next-gen Fabric platforms.
SOC Physical Design Engineer (12 month contract)
Designs and optimizes physical layouts for System-on-Chip (SoC) designs, using tools like floor-planning, place-and-route, and scripting in Perl/TCL/Python.
Digital IC Design Engineer (New Grad)
Design and implement digital and mixed-signal chips for power management and automotive systems using ASIC tools, synthesis, and verification.
Senior FPGA Design Engineer
Designs and implements FPGA-based prototypes for ASIC validation using Verilog, high-speed interfaces, and Quartus Prime Pro, collaborating with cross-functional teams to optimize timing and debug hardware.
Testchip Design & Implementation Intern (Jan-Jun 2027)
An intern explores AI and automation tools to improve semiconductor testchip design workflows, collaborating with engineers and documenting findings for future implementation.
Physical Design Engineer ICE
Design and verify advanced chip layouts for Intel, focusing on cell/block-level layouts, floor planning, and full-chip assembly to ensure high-performance chip functionality.
SOFTWARE ENGINEER
Design, implement, and support software solutions for semiconductor manufacturing automation, using languages like Perl, Linux, and optionally Python or C/C++. Provide 24/7 global support and improve IT roadmaps.
EE Assist. Manager/Supervisor 硬體研發副理/課長 - ISG (iSystem/ 內湖陽光)
【職務概要】 本職位負責 Modular IPC、Industrial PC等電腦產品之硬體研發與團隊管理，從客戶需求、產品規格定義、硬體架構規劃、電路設計、設計驗證至量產導入，主導完整產品開發流程。 我們期待此職位除了具備團隊管理與專案推動能力外，同時具備扎實的硬體實作能力，能實際參與 Schematic Design、Layout Review、系統整合與問題 Debug，並能與客戶、PM…