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Embedded Software Engineer
Develop, debug, and test embedded software for bare-metal, RTOS, and Linux-based avionics systems, collaborating with hardware engineers to deliver flight-quality software for space and defense applications.
Senior Principal FPGA & Digital Signals Processing Engineer
Lead FPGA firmware architecture for a portable SIGINT/EW platform, migrating GPU DSP algorithms to FPGA and optimizing real-time RF signal processing for defense missions.
FPGA Software Entwickler für Video / Bildverarbeitung (m/w/d)
Develops FPGA-based video/image processing pipelines in VHDL/Verilog, integrates with C/C++ and Python, and collaborates with software teams to deploy embedded vision systems for industrial, medical, and rugged applications.
Silicon Design Engineer
Design and verify ASIC and semiconductor components for AMD’s next-gen processors, using Verilog/VHDL, EDA tools, and Unix/Linux workflows.
Analog Designer
Designs and tests high-speed analog and mixed-signal circuits (GDDR, PLLs, SerDes) for next-gen AMD processors using Verilog, C++, and Cadence tools.
Sr. Silicon Design Engineer
Design and verify next-gen GPU/CPU/SoC silicon, writing RTL in Verilog/SystemVerilog/VHDL and using ASIC tools to optimize power, timing, and area for AMD processors.
MTS Silicon Design Engineer
Design and verify ASICs and SoCs for next-gen processors using Verilog, VHDL, and UVM testbenches in a distributed compute environment.
Sr. Silicon Design Engineer
Design and verify next-gen ASICs and SoCs for AMD/Xilinx chips using RTL, Verilog/SystemVerilog/VHDL, and C/C++/Python in Linux environments.
Sr. Silicon Design Engineer
Design and verify next-gen ASIC/SOC components for AMD’s processors using Verilog/VHDL, SystemVerilog, UVM, and PCIe/AXI protocols.
Silicon Design Engineer
Design and verify ASIC components for next-gen processors using RTL, Verilog/VHDL, and EDA tools while optimizing CPU architecture and memory management.
MTS Silicon Design Engineer
Design and verify next-gen CPU/GPU/SoC silicon, writing Verilog/SystemVerilog tests and collaborating with RTL teams to debug pre-silicon issues.
Sr. Silicon Design Engineer
Design and verify next-gen semiconductor components for AMD’s processors, focusing on ASIC, GPU, and SOC architecture using Verilog/VHDL, RTL, and EDA tools.
Silicon Design Engineer
Design and verify ASIC components for next-gen processors using Verilog/System Verilog and RTL coding in a Linux environment.
Sr. Silicon Design Engineer
Design and verify next-gen semiconductor components and ASICs using Verilog/VHDL, CMOS, and EDA tools in a Linux environment.
Sr. Silicon Design Engineer
Design and verify next-gen semiconductor chips using Verilog, SystemVerilog, VHDL, and EDA tools; develop hardware verification flows and write Python/C++/Shell scripts.
MTS Silicon Design Engineer
Designs and verifies next-gen CPU hardware using C++, Verilog, and UVM; runs simulations and formal checks to catch bugs before silicon tape-out.
Silicon Design Engineer
Design and verify next-gen CPU/GPU/SoC components using Verilog/SystemVerilog/VHDL, C/C++, and Python in Linux environments.
Sr. Silicon Design Engineer
Design and verify next-gen CPU/GPU/APU silicon, writing Verilog/SystemVerilog/VHDL and C/C++/Python to architect and simulate complex ASICs for AMD’s processors.
Sr. Silicon Design Engineer
Design and verify next-gen semiconductor chips using C/C++/Python and HDLs like Verilog/SystemVerilog; drive ASIC flows from RTL to synthesis, place-and-route, timing, and power analysis.
Sr. Silicon Design Engineer
Design and verify next-gen CPU/GPU/SoC components using Verilog/SystemVerilog/VHDL and C/C++/Python for AMD’s semiconductor products.