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Software Engineer (C++)
Software Engineer II (C++) Location: FELDKIRCHEN (Munich), CAMBRIDGE 03 Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.…
Assistant Real-Time Embedded Software Engineer
Assistant Real-Time Embedded Software Engineer Location: Pittsburgh, PA Time Type: Full time Job Description SEI advances software engineering principles and practices and serves as a national resource in software…
Embedded Engineer
Embedded Engineer Department: Damba Tech Location: Kyiv Employment Type: FullTime Шукаємо кандидатів на позицію Embedded Engineer в українській інженерній компанії, що спеціалізується на розробці та виробництві засобів…
Hardware Engineer Intern
Hardware Engineer Intern - Summer 2027 Location: Chicago, United States Department: Development (Group) Our 10-week internship is your chance to experience life as a Hardware Engineer at IMC. You’ll have the support…
Graduate Hardware Engineer
Graduate Hardware Engineer Location: Chicago, United States Department: Development (Group) Having the best technology drives our business. As a Hardware Engineer at IMC, you are responsible for spotting new…
FPGA Verification Engineer
FPGA Verification Engineer Level 3/4 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR…
FPGA Verification Engineer
FPGA Verification Engineer Level 5 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START:…
Micro-architect/Logic Designer, Coherent Interconnect
Designs and optimizes high-performance coherent interconnect IP and last-level cache blocks for Samsung's advanced semiconductor products, collaborating with architects, verification, and implementation teams.
CPU Micro-architect
Designs and optimizes high-performance CPU cores for AI, computing, and edge devices, focusing on microarchitecture, performance modeling, and silicon correlation.
Design Verification Engineer, Coherent Interconnect
Designs and verifies high-performance coherent interconnect IP for Samsung’s SoCs, using SystemVerilog/UVM and ARM protocols to ensure low-latency, power-efficient solutions for next-gen mobile devices.
Logic Design Engineer
Designs and optimizes high-speed digital logic for AMD’s mixed-signal IO interfaces, using Verilog RTL and ASIC flows to deliver silicon-ready solutions.
Manager, ASIC Design Engineering (Starshield Silicon)
Lead a team designing ASICs and FPGAs for SpaceX’s Starshield satellite systems, overseeing RTL implementation, verification, and silicon bring-up to deliver high-speed data processing for national security missions.
Principal ASIC Design Engineer (Starshield)
Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog and collaborating with verification and physical implementation teams.
Sr. ASIC Design Engineer (Starshield)
Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog, EDA tools, and collaborating with verification and physical implementation teams.
FPGA/ASIC Design Engineer (Silicon Engineering)
Designs and optimizes FPGAs and ASICs for SpaceX's Starlink network, using Verilog/SystemVerilog and collaborating with cross-functional teams to enhance satellite and ground infrastructure performance.
RTL Design Engineer (Silicon Engineering)
Designs and implements FPGAs and ASICs for SpaceX's Starlink network using Verilog/SystemVerilog, collaborating across teams to enhance satellite and ground infrastructure connectivity.
Sr. RTL Design Engineer (Silicon Engineering)
Designs and implements high-performance ASICs in Verilog/SystemVerilog for SpaceX’s Starlink network, collaborating with cross-functional teams to deliver space-grade silicon for global connectivity.
Sr. RTL Design Engineer (Silicon Engineering)
Designs and implements high-performance ASICs in Verilog/SystemVerilog for SpaceX’s Starlink network, collaborating with cross-functional teams to deliver space-grade chips that enable global broadband connectivity.
Senior Design Verification Engineer
Senior engineer builds and automates hardware verification environments for Microsoft’s cloud silicon, using emulation platforms like Zebu and Palladium to validate SoC designs before manufacturing.
AI Silicon, Junior Digital Design Engineer
Junior Member of Technical Staff - AI Silicon Digital Design Engineer About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental…