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Research and Development Software Developer
Develop and maintain signal-processing software for defense research, implementing algorithms in Python and MATLAB for underwater acoustic data analysis and deployment.
VLSI Design Engineer
We are looking for talented and experienced VLIS Design Engineers/Micro-architects. As an VLIS Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting…
Factory Data Analytics Engineer
Builds factory data analytics tools and visualizations to improve test yields and process control for aerospace/defense manufacturing using Python, SQL, and JavaScript frameworks.
Middleware Service Operations Specialist
Key Responsibilities Provide production operations and technical support for middleware technologies and platforms. Maintain the reliability, availability and stability of middleware services. Troubleshoot, analyse and…
Senior Java Developer
Lead engineering teams to build ultra-low-latency Java trading platforms for Barclays’ Equities DMA systems, optimizing performance and scalability for high-volume institutional trading.
Test Engineer
Designs and runs test scenarios for embedded devices and systems, automates tests, logs defects, and works with devs to improve product reliability.
Performance Test Engineer
Design and run performance tests for DTCC’s financial-market systems, analyze bottlenecks with tools like JMeter and Dynatrace, and automate tests in a CI/CD pipeline.
Experienced Firmware Engineer – Fixed Dome Cameras
Develop and maintain firmware for Axis network video cameras, adapting AXIS OS (Linux-based) and solving embedded Linux challenges to power next-gen security devices.
Cloud Engineer (Advisor)
Designs, builds, and secures cloud infrastructure (AWS/Azure/GCP) and mentors teams to support scalable, mission-critical systems for housing finance.
ASIC/FPGA Design Engineer
Design and verify ASIC/FPGA logic for high-speed networking hardware using Verilog/SystemVerilog, and collaborate on bring-up and validation.
Performance Test Engineer
Design and run performance tests for DTCC’s financial-market systems, analyze bottlenecks with tools like JMeter and Dynatrace, and automate tests in a CI/CD pipeline.
Sr. Systems Engineer, Integration & Test Engineer
Designs and runs integration, verification, and regression tests for radar systems in a hardware-in-the-loop lab, analyzes performance data, and supports software builds for defense radar programs.
Systems Administrator II (Unix / Linux)
Maintains and automates Red Hat Linux servers and workstations, writes bash/Ansible scripts, configures SAN storage, and ensures security compliance for a government contractor.
New College Grad - IT Software Support Engineer
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Cloud Engineer - TS/SCI with Polygraph
Design, deploy, and secure cloud infrastructure for a government cyber-security customer using AWS/Azure, Kubernetes, and CI/CD pipelines.
Cloud Engineer - TS/SCI with Polygraph
Design, deploy, and secure cloud infrastructure for a government cybersecurity customer using AWS/Azure, Kubernetes, and CI/CD pipelines.
SRE/Production Support Lead
Lead a team to monitor, troubleshoot, and stabilize Morgan Stanley’s Wealth Management Investment Management platforms, ensuring high availability and resolving production issues with DevOps/SRE practices.
Lead Engineer - Design Verification (Low power UPF/CPF)
Lead a team verifying low-power features in complex SoC designs using UPF/CPF methodologies, building SystemVerilog/UVM testbenches and driving coverage closure.
Staff Engineer - IC Design
Designs and implements reusable digital IP blocks (Verilog/SystemVerilog) for low-power wireless SoCs, focusing on PPA targets and AMBA/peripheral IP like SPI, UART, and DMA.
Lead Engineer – IC Design (STA Lead )
Lead a team to implement and sign off on timing constraints, synthesis, and static timing analysis for high-performance SoCs and ASICs using Cadence or Synopsys EDA tools.