Tech jobs
Job listings
CPU Server Physical Design Timing Engineer
Design and optimize timing constraints for Qualcomm’s Oryon CPU cores using industry tools like PrimeTime and Tempus, scripting in TCL/Python, and collaborating with RTL and implementation teams.
CPU RTL Design Engineer
Design and implement CPU microarchitecture and RTL for high-performance, low-power devices, collaborating with architects and verification teams.
IC Design Engineer
Designs and verifies analog and mixed-signal ICs to emulate obsolete microcircuits for defense systems, using tools like Verilog/VHDL and Python.
Radar System Analyst
Analyzes and optimizes radar system performance for missile warning radars, reducing track data, diagnosing anomalies, and refining operational procedures to ensure mission readiness.
Staff Software Quality Assurance Engineer
Designs and runs automated and manual tests for embedded storage software, writes test plans in C/C++, and tracks bugs in JIRA to ensure product quality.
Functional and Performance Verification Architect
Architect next-generation pre-silicon verification strategies for complex semiconductor designs, leading simulation, formal, and emulation methodologies to ensure first-pass silicon success.
Microprocessor VLSI Physical Design Engineer
Designs high-speed VLSI circuits for next-gen CPU cores and caches using deep submicron FinFET processes, optimizing power, performance, and area while collaborating across teams.
Product Development Architect
Lead a team to implement and tape out high-performance ASIC/APU/dGPU designs for AI, gaming consoles, and automotive using RTL-to-GDS flows, PnR, timing closure, and physical verification.
Senior Design Verification Engineer
Senior engineer verifying complex processor designs using SystemVerilog/UVM, formal tools, and coverage-driven flows to ensure functional correctness of Network-on-Chip IPs and SoCs.
Infrastructure Firmware Engineer
Lead end-to-end delivery of firmware infrastructure for AMD’s CPUs/GPUs, including design, validation, and CI/CD automation in C/C++ and cloud environments like Azure and Kubernetes.
Analog Designer
Designs and verifies custom IC layouts for analog and digital circuits using Cadence Virtuoso and Mentor Calibre, including PLLs, DACs, and high-speed signaling blocks.
Embedded Software Intern
Intern develops embedded C/C++ software for microcontrollers on Linux-based systems, integrating and testing modules for Bosch’s global projects.
DevOps Intern
Internship role automating software engineering workflows using Python, Jenkins, and CI/CD pipelines for embedded systems at a global tech supplier.
Senior/Staff Subsystem & SoC Design Engineer
Designs and verifies GPU and control subsystems for AI-focused SoCs, integrating Arm IP and third-party components for edge, physical, and cloud AI applications.
EDA (Electronic Design Automation) Engineer
Build and optimize electronic design automation tools and flows for semiconductor teams using Python and AI-assisted scripting to improve design efficiency and time-to-market.
Physical Design Engineer
Designs and optimizes advanced semiconductor IP and SoCs from RTL to GDSII, focusing on timing closure, power reduction, and physical verification for next-gen FPGAs.
Senior Physical Design Engineer
Senior engineer who implements custom IP and SoC designs from RTL through GDSII, closing timing, optimizing power, and signing off on next-gen FPGA silicon using Synopsys/Cadence EDA tools.
Director, Embedded Memory
Lead a team to design and deliver embedded memory compilers (SRAM, ROM, register files, DPRAM) across process nodes, setting technical direction and driving PPA optimization while serving as the senior technical voice in customer engagements.