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Senior Engineer, FPGA
Designs and implements FPGA-based digital signal processing systems for high-precision analytical instruments using Verilog/VHDL and Xilinx tools in Santa Clara, CA.
Design Verification Lead
Leads verification of cutting-edge FPGA and ASIC solutions for PCIe and CXL-based IP, collaborating with global teams to ensure first-pass silicon success using UVM and SystemVerilog.
FPGA Digital Design Engineering Intern (January 2027) (4-16 months)
At Kepler Communications , we're not just imagining the future of on-demand space connectivity - we're leading it! Our mission is to provide real-time on-orbit connectivity for critical missions, enabling a new…
Senior FPGA Designer
Designs and optimizes ultra-low-latency FPGA hardware and networking IP for financial trading systems, using VHDL/Verilog and tools like Xilinx Vivado.
Principal Silicon Design Engineer
Principal Silicon Design Engineer designs high-performance SoC components for Microsoft's AI systems, using Verilog/SystemVerilog, RTL, and clock/reset domain checks.
Principal Engineer - Design Verification
Principal Engineer responsible for verifying complex microcontroller and microprocessor designs using UVM, SystemVerilog, and EDA tools to ensure correct, safe, and secure SoC functionality.
Design Vision Lead, Edge AI, Google Cloud
Leads a team designing custom silicon and edge AI hardware for Google's products, using SystemVerilog and RTL development to optimize performance and integration.
FPGA Software Entwickler für Video / Bildverarbeitung (m/w/d)
Develops and adapts FPGA-based video processing pipelines, implements designs on hardware, and collaborates with software teams using VHDL/Verilog, C/C++, and Python.
Senior/Staff Design Verification Engineer (SOC)
Design Verification Engineer at Bitdeer in Singapore, responsible for verifying complex digital ASIC designs using UVM, SystemVerilog, and industry tools to ensure functional correctness and silicon quality.
Senior/Staff Front-End Engineer (IP Integration)
Develops and integrates PCIe IP blocks using Verilog RTL for a Bitcoin mining and AI cloud company, ensuring functional coverage and collaborating with verification and software teams.
Senior/Staff Front-End Design Engineer (RTL Design - RiscV)
Designs and integrates RISC-V CPU cores with custom extensions for ASIC chips in Bitcoin mining and AI cloud hardware, using Verilog/SystemVerilog and collaborating with cross-functional teams.
Sr. RTL IP Design Engineer
Designs and integrates high-performance networking IP blocks for data center solutions, collaborating with architecture and physical design teams to ensure first-pass silicon success.
Senior/Staff Design Verification Engineer
Design Verification Engineer at Bitdeer in Singapore who builds and runs test environments for ASIC chips and AI cloud hardware using UVM, SystemVerilog, and formal tools to ensure functional correctness before silicon.
Senior/Staff Front-End Engineer (RTL Design)
Designs and implements RTL (Verilog HDL) for ASIC chips, including microarchitecture, IP integration, and collaboration with verification/implementation teams for tape-out.
Avionics Engineer I - Design
Designs and tests flight-quality electronics for spacecraft avionics, including power systems and control circuits, using tools like Altium Designer and LTspice.
Contract FPGA Engineer
Contract FPGA Engineer required to carry out one of two interesting firmware projects for this company in Didcot. Skills in order of importance for the Contract FPGA Engineer: FPGA programming in Verilog or VHDL SoC…
Digital Design Engineer, RTL IP, Silicon
Designs and integrates custom silicon IP for Google's hardware products, focusing on RTL design, bus protocols, and SoC milestones.
Principal Engineer, ASIC Design
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…