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Sr. Staff/Staff Design Verification Engineer
Design Verification Engineer at Cerebras, building and testing the world's largest AI chip to ensure first-silicon success and ultra-fast AI inference.
Design Verification Engineer
Design Verification Engineer at AMD responsible for verifying custom hardware accelerators for servers, datacenters, and client/embedded markets using advanced ASIC verification techniques and methodologies like UVM and formal verification.
Analyst, Infrastructure Observability
Build and maintain global log and monitoring infrastructure for financial markets tech, using APM tools like Datadog and Splunk to track network and app anomalies across data centers.
SOFTWARE ENGINEER with Security Clearance
Senior Software Engineer building and maintaining Java-based web applications for a government cybersecurity team with active TOP SECRET/SCI clearance.
Senior Engineer, CMOS & Metallization Test Structure Design and Layout
Designs and lays out CMOS and metallization test structures for semiconductor R&D, using EDA tools like Cadence Virtuoso and Calibre to enable DRAM/NAND process development and reliability analysis.
Verification Enablement, Test Structure Design and Layout
Design and automate physical verification flows for semiconductor scribe designs, coding rule decks in Calibre SVRF/TVF and scripts in Python/Perl to validate PDK updates and IC layout.
Design Verification Engineer
Design Verification Engineer at NXP Semiconductors in Catania; builds and runs UVM/SystemVerilog test benches to validate complex semiconductor designs.
Junior Design Verification Engineer
Junior engineer verifying semiconductor designs using SystemVerilog, UVM, and simulation tools to ensure functional correctness and reliability.
Senior Software Engineer
Build and maintain full-stack manufacturing applications using C#, .NET, and cloud services, while leveraging AI tools to improve code quality and productivity.
Site Reliability Engineer
Build and maintain CI/CD pipelines and automation for Mastercard’s BizOps team to improve reliability, deployment, and incident response in a large-scale fintech environment.
IP Verification Engineer - Digital Design Verification
Design and run verification testbenches for DRAM memory blocks using SystemVerilog/UVM, analyze coverage, and debug failures to ensure tapeout readiness.
GPU Performance Architect
Architect GPU performance by analyzing bottlenecks in high-end SoCs and GPUs, modeling hardware at multiple abstraction levels, and optimizing for graphics, ML, and automotive workloads.
Senior Firmware Architect, RAS and Power Management
Architect and implement firmware for reliability, availability, serviceability, and power management across NVIDIA’s networking platforms, collaborating with hardware, software, and validation teams.
Design-for-Test Engineer
Design-for-Test Engineer at NVIDIA develops test architectures and methodologies for complex semiconductor chips, including scan compression, memory/IO BIST, and post-silicon validation.
Mission Planner/Orbital Analyst
A Mission Planner/Orbital Analyst supports experimental satellite systems, performing pre-launch and on-orbit mission planning, interfacing with payload customers, and developing mission documentation, using orbital mechanics and scripting languages like Python and C++.
Full Stack Java Application Developer
Build and maintain scalable Java/Scala systems for risk analytics and trading infrastructure, partnering with traders and quants to deliver high-performance distributed solutions.
Senior Software Engineer
Senior Software Engineer modernizes enterprise infrastructure platforms using Python, Perl, Linux, and VMware, while automating CI/CD pipelines and server environments.
Mixed Signal Design Verification Engineer
Design and verify mixed-signal system-on-chip circuits for wireless applications using SystemVerilog, VerilogAMS, and Python.