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ASIC/FPGA Mid-Level Manager - Design & Verification
Manage a team designing and verifying ASIC/FPGA chips for aerospace and defense programs, ensuring first-pass quality and on-time delivery while mentoring engineers.
Asic RTL Design Engineer
Design and implement synthesizable RTL for complex ASIC/SoC using Verilog/SystemVerilog, focusing on Lint, CDC, and SoC integration while collaborating with cross-functional teams.
Principal Design Verification Engineer, HBM
Lead verification of high-bandwidth memory (HBM) and DRAM designs using SystemVerilog/UVM, ensuring functional correctness and performance for Micron’s memory products.
IC Design Engineer
Designs and implements RTL code and micro-architectures for digital IPs and SoCs in the automotive domain, following the full ASIC flow.
Senior CPU RTL Design Engineer, Power Management
Designs power-efficient CPU microarchitectures and RTL blocks in SystemVerilog/Verilog, focusing on DVFS, power states, and CDC to optimize PPA for next-gen processors.
Senior CPU Design Verification Engineer
Senior engineer verifying CPU and SoC designs using SystemVerilog/UVM to catch bugs before silicon, collaborating with architects and RTL teams to ensure correct, power-efficient performance.
Principal ASIC Design Engineer
Lead the design of next-gen ASIC IP for AI-driven data movement, collaborating across teams to deliver high-performance, secure, and power-efficient silicon solutions for AMD’s server, data center, and embedded products.
Staff Engineer, VLSI Design Engineering
Lead verification of complex SoC designs using UVM, SystemVerilog, and formal tools to ensure memory chips meet specifications before tape-out.
GPU RTL Design Engineer
Designs and implements GPU hardware in Verilog/SystemVerilog, optimizing for performance, power, and area while collaborating with verification teams.
Design Verification Engineer - Fully Remote | Upto $175/hr
Design Verification Engineer builds and verifies RTL components in Verilog/SystemVerilog to improve AI model training and evaluation workflows, using UVM and LLM-based tools.
FPGA Engineer
Designs, verifies, and tests FPGA-based RTL for satellite systems, collaborating with hardware, software, and DSP teams to meet performance and radiation-mitigation requirements.
ASIC/FPGA Verification engineers
Design and run verification environments for ASIC/FPGA chips using SystemVerilog/UVM, then execute test cases to ensure hardware correctness.
Software Engineer, GenAI Silicon Automation, DeepMind
Build AI-driven infrastructure to automate silicon design workflows, using MLIR/CIRCT and agentic systems to bridge ML models with hardware accelerators.
Senior SoC and IP Design Engineer, Google Cloud
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Design Verification Engineer, Networking, Google Cloud
Verify custom silicon designs for Google Cloud, building constrained-random test environments in SystemVerilog/UVM to uncover bugs and ensure tape-out readiness.
Staff Engineer, VLSI Design Engineering (SOC Verification, UVM) with 8 to 12 years of experience
Lead verification of complex SoC designs using UVM, SystemVerilog, and formal tools; develop test plans, coverage-driven environments, and automation to validate NAND flash memory subsystems.
Experienced Engineer - FPGA CAD
Build and maintain FPGA CAD tools and automation flows in Python/Tcl to speed up synthesis, place & route, and verification for Ericsson’s radio/RAN compute products.
Experienced Engineer - FPGA Verification
Designs and implements FPGA verification environments for 5G/6G radio and compute products using SystemVerilog, UVM, and industry tools.
Experienced Engineer - ASIC Design
Design ASIC IP blocks and subsystems for 5G/6G mobile networks using SystemVerilog, AMBA protocols, and RTL sign-off tools.
SC Cleated FPGA Engineer
Designs and implements FPGA firmware for AMD/Xilinx Zynq UltraScale MPSoC using Vivado, HDLs, and embedded Linux tooling (Yocto/PetaLinux) in a Central London office.