Tech jobs
Job listings
ASIC Design Engineers to our R&D site in Stockholm
Design and develop ASIC hardware for Axis’s ARTPEC SoC chips, focusing on digital logic, HDLs (SystemVerilog), and EDA tools to power surveillance cameras.
Principal Physical Design
Principal Physical Design Engineer leads DRAM digital design implementation from RTL to tapeout, focusing on timing closure, power integrity, and reliability while mentoring teams and driving methodology innovation.
Design-for-Test (DFT) Engineer
Owns design-for-test (DFT) strategy for complex ASIC/SoC chips, implementing scan, ATPG, and test compression to maximize fault coverage and silicon yield.
Physical Design Engineer
Designs and optimizes ASIC physical layouts using Cadence Innovus, closing timing and power targets for complex chips.
Sr FPGA Firmware Engineer
Designs and verifies FPGA-based control logic for aerospace engine controllers and avionics, using VHDL/Verilog and tools like Xilinx Vivado.
Technical Staff Engineer - Design
Design engineer role building next-gen storage and memory controller SoCs, owning IO/pad-ring planning and physical-design hand-off for high-performance data-center products.
Digital Thread Architect
Design and implement Digital Thread solutions connecting Siemens Teamcenter, ERP, MES, and other enterprise systems to improve data continuity and automation across engineering and manufacturing workflows.
IC Design Engineer
Designs and implements RTL code and micro-architectures for digital IPs and SoCs in the automotive domain, following the full ASIC flow.
Technical Manager, IC Physical Design
Leads physical design of cutting-edge 6nm/4nm/3nm chips, coordinating synthesis, floorplanning, and tapeout for large hierarchical SoCs.
Principal ASIC Design Engineer
Lead the design of next-gen ASIC IP for AI-driven data movement, collaborating across teams to deliver high-performance, secure, and power-efficient silicon solutions for AMD’s server, data center, and embedded products.
FPGA Engineer
Designs, verifies, and tests FPGA-based RTL for satellite systems, collaborating with hardware, software, and DSP teams to meet performance and radiation-mitigation requirements.
ASIC/FPGA Verification engineers
Design and run verification environments for ASIC/FPGA chips using SystemVerilog/UVM, then execute test cases to ensure hardware correctness.
CPU Design for Testing Engineer
Designs and deploys test solutions for next-gen CPUs, collaborating with RTL, PDTE, and SiVal teams to ensure flawless silicon delivery and high test coverage.
Experienced Engineer - FPGA CAD
Build and maintain FPGA CAD tools and automation flows in Python/Tcl to speed up synthesis, place & route, and verification for Ericsson’s radio/RAN compute products.
Experienced Engineer - FPGA Verification
Designs and implements FPGA verification environments for 5G/6G radio and compute products using SystemVerilog, UVM, and industry tools.
Senior Engineer - FPGA Design
Designs and optimizes FPGA-based solutions for radio and RAN compute systems, integrating hardware/software components using HDL and industry tools like Vivado or Quartus.
Experienced Engineer - ASIC Design
Design ASIC IP blocks and subsystems for 5G/6G mobile networks using SystemVerilog, AMBA protocols, and RTL sign-off tools.
Principal Physical Design Engineer
Principal engineer designing and optimizing physical layouts for Microsoft's next-gen AI chips, ensuring high-performance, low-power, and manufacturable designs using industry-standard EDA tools.
Avionics FPGA Engineer
Design and verify FPGA-based avionics for autonomous space systems using SystemVerilog/Verilog, debug hardware in the lab, and collaborate on flight-ready systems.