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Physical Design Engineer
Design and implement complex ASIC/SOC physical layouts using Synopsys tools like Fusion Compiler or ICC2, debug timing/congestion issues, and mentor junior engineers.
Associate Software Engineer
Develops embedded software for tactical radio systems, working across the full SDLC with languages like C++, Python, and Qt on real-time OS platforms.
Software Engineer
Develops and tests embedded software for tactical radio systems, working across the full SDLC with C++, Python, and real-time OS platforms.
Associate Software Engineer
Develops embedded software for tactical radio systems, working across the full SDLC with languages like C++, Python, and VxWorks on real-time OS platforms.
Senior/Staff Front-End Engineer (SOC)
Design and implement Verilog RTL for SoC blocks, integrate IPs, and optimize performance through synthesis, timing closure, and power reduction in a semiconductor R&D team.
ASIC Design Verification Engineering Leader
Lead verification of Cisco’s cutting-edge data-center ASICs, building DV environments, writing test plans, and ensuring full coverage with Verilog/SystemVerilog/UVM while collaborating with designers and software teams.
Lead, Site Reliability Engineer
Lead a team to ensure the reliability of Mastercard’s real-time payment platforms, driving automation, incident response, and DevOps best practices for 200+ countries.
(Fresh Grads Welcome) IT Infrastructure Engineer
Maintains and secures Windows/Linux servers, VMs, networks, and storage; troubleshoots issues and automates tasks with scripting.
Design-for-Test (DFT) Engineer-Singapore
Design-for-Test engineer implements chip-level testability features (scan, MBIST, ATPG) and debugs DFT-related timing/power issues to ensure silicon test success.
Java Architect | Contract
Java architect designs and deploys Saviynt Identity Governance solutions, builds connectors, and leads technical teams to integrate IAM systems with enterprise apps.
Design Verification Engineer
Design Verification Engineer at Texas Instruments in Knoxville builds and runs test benches to verify analog and mixed-signal ICs, ensuring first-pass silicon success for industrial, automotive, and consumer applications.
Design Engineer -Memory Layout
Job Overview: This opening is for a memory layout designer in our PHYSICAL IP – MEMORY group in Noida. We work on innovative memory architectures in pioneering technology nodes to enable the best Arm Systems in all the…
Designer, Systems (Computer)
Designs and implements high-performance RISC-V CPU and SoC RTL modules using SystemVerilog, collaborating with architects, verification, and backend teams to optimize performance, power, and area.
Lead Support Analyst, Market Connectivity, IT
Position Description This role will be part of the Global Market Connectivity team responsible for supporting Exchange Connectivity systems for various exchanges and servicing Market Data applications. Working closely…
Production Support Analyst
Experience : 6-9 Years Role : Production Support Analyst Key Skills: Strong skills in Unix / Linux, Perl / Shell scripting, Database (MSSQL Oracle, Sybase) BMC Control-M Scheduler Knowledge in Temenos TripleA and…
IC package design engineer
Job Description Meet the Team Join the Package Design Team at Cisco Silicon One in Armenia, a group leading the way in developing Cisco's groundbreaking silicon solutions for next-generation networking. As a…
Design Verification Engineer
Design Verification Engineer builds and runs test environments for complex ASIC and mixed-signal IP using SystemVerilog/UVM, coverage analysis, and debug to ensure correctness before tape-out.
Senior/ IC Design Engineer (Physical Design)
Designs and implements ASIC physical design flows (RTL-to-GDS) using EDA tools and AI-assisted methodologies to optimize PPA and timing for tape-out.
Hardware Power Engineer (Networking)
Design and validate power delivery systems for next-gen networking hardware, selecting components, debugging boards, and ensuring robust performance in HPE’s R&D team.