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Senior Design Verification Engineer
Senior engineer builds and runs pre-silicon verification environments and tests for Microsoft’s AI accelerators, collaborating with architects and firmware teams to ensure silicon quality before tape-out.
Software Developer (Entry-Level) at ASRC Federal
Develop and maintain air-traffic control software using C/C++, Java, SQL, and Python; write tests and support the FAA’s STARS system in Egg Harbor Township, NJ.
US_East | Software Developer - Client Server_L4
Develops and maintains embedded infotainment software for Linux and Android in automotive systems, focusing on graphics, audio, and networking stacks.
Senior Security IP Engineer
Designs and validates security IP blocks (e.g., cryptographic accelerators, root-of-trust) for Microsoft’s cloud hardware, collaborating with SoC and firmware teams to deliver secure, high-performance RTL solutions.
Fellow Architect, Functional & Performance Verification
Lead AMD’s pre-silicon verification strategy, defining next-gen architectures and methodologies to ensure first-pass silicon success for complex SoC designs using advanced EDA tools and ML/AI innovations.
Mid Level - Backend Software Engineer
Mid-level backend engineer in Laurel, MD designing and building cloud-based web services and APIs using Python, Docker/Kubernetes, and AWS, while contributing to full-stack development and DevOps practices.
Software Engineer
Develops and maintains software systems for a national security customer in Hanover, MD, using Java, Spring, JavaScript, and related enterprise tools.
Hardware Design Engineer - Level 3
Designs and tests integrated circuits, ASICs, and FPGAs for signal processing; reverse-engineers hardware/firmware using VHDL, Xilinx tools, and Linux.
Linux System Administrator (m/w/d)
Administers and automates Linux infrastructure for government clients, using SUSE, Puppet, Ansible, and scripting to maintain and scale systems.
Backend Developer
Build and maintain secure backend systems for U.S. Navy aviation logistics using Java, C/C++, and JBoss in a DoD environment.
Peripherals Design Verification Engineer
Designs and verifies peripheral IP blocks (PCIe, CXL, USB, Ethernet) using SystemVerilog/UVM, coverage-driven random testing, and C-based reference models.
WLAN RTL Design Senior Engineer
Designs next-gen WLAN hardware at the RTL/IP level, focusing on logic synthesis, timing constraints, and low-power optimization for 6nm+ processes using tools like Genus, Primetime, and Tcl scripting.
Implementation Timing / STA Design Engineer
Implementation Timing / STA Design Engineer Location: San Diego, California, United States of America Department: ASICS Engineering Work Location: onsite Company: Qualcomm Technologies, Inc. Job Area: Engineering…
Staff Design Verification Engineer
Design verification engineer building UVM testbenches for high-speed interconnects (PCIe, CXL, AXI) to ensure ASIC/subsystem correctness before tape-out.
Silicon Physical Design STA Lead, Google Cloud
Lead a team to perform Static Timing Analysis (STA) on Google’s custom silicon SoCs, ensuring timing closure and low power for AI accelerators while collaborating with architecture and physical design teams.
Staff Test Engineer
Designs and executes test plans for GPON/XGS-PON broadband hardware, validating L2/L3 protocols and OLT/ONT devices using Python automation and tools like Spirent/Ixia.
Modem System Test Engineer, 6G/5G Air Interface
Test and validate next-gen 5G/6G modem systems, analyzing PHY/MAC layers and RF performance to ensure global commercialization of Qualcomm’s wireless chips.