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FPGA Engineer
Designs, verifies, and tests FPGA-based RTL for satellite systems, collaborating with hardware, software, and DSP teams to meet performance and radiation-mitigation requirements.
ASIC/FPGA Verification engineers
Design and run verification environments for ASIC/FPGA chips using SystemVerilog/UVM, then execute test cases to ensure hardware correctness.
CPU Design for Testing Engineer
Designs and deploys test solutions for next-gen CPUs, collaborating with RTL, PDTE, and SiVal teams to ensure flawless silicon delivery and high test coverage.
Experienced Engineer - FPGA CAD
Build and maintain FPGA CAD tools and automation flows in Python/Tcl to speed up synthesis, place & route, and verification for Ericsson’s radio/RAN compute products.
Experienced Engineer - FPGA Verification
Designs and implements FPGA verification environments for 5G/6G radio and compute products using SystemVerilog, UVM, and industry tools.
Senior Engineer - FPGA Design
Designs and optimizes FPGA-based solutions for radio and RAN compute systems, integrating hardware/software components using HDL and industry tools like Vivado or Quartus.
Experienced Engineer - ASIC Design
Design ASIC IP blocks and subsystems for 5G/6G mobile networks using SystemVerilog, AMBA protocols, and RTL sign-off tools.
Principal Physical Design Engineer
Principal engineer designing and optimizing physical layouts for Microsoft's next-gen AI chips, ensuring high-performance, low-power, and manufacturable designs using industry-standard EDA tools.
Avionics FPGA Engineer
Design and verify FPGA-based avionics for autonomous space systems using SystemVerilog/Verilog, debug hardware in the lab, and collaborate on flight-ready systems.
Digital Design Engineer
Designs and debugs RTL for AMD’s Infinity Data Fabric, optimizing for power, timing, and area while collaborating with global teams.
PLM Software Developer
Develop and customize PLM software integrations for clients in automotive, aerospace, energy, and machinery, focusing on engineering design and manufacturing workflows.
RTL Design Engineer – FPGA High-Speed Connectivity IP
Design and validate high-performance RTL IPs for FPGA high-speed connectivity subsystems using VHDL/Verilog and AMD/Xilinx toolchains.
PLL Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Mask Layout Designer
Designs and verifies advanced semiconductor mask layouts for high-performance processors, collaborating with circuit teams to ensure tape-out readiness using industry-standard tools.
Senior Silicon Design Engineer
Design and optimize clocking and physical design flows for complex SoC/ASIC chips using industry-standard EDA tools and scripting.
Physical Design Engineer
Designs and implements physical layouts for high-performance chip IP, owning floorplanning through GDS tape-out on advanced nodes (28nm or below).
Design Verification Principal Engineer
Principal Engineer designs and verifies memory controller IP for DDR/HBM/GDDR DRAM, building SystemVerilog testbenches and coverage-driven regression suites.
Design Verification Engineer, PCIe Controller
Design Verification Engineer for PCIe and CXL controller IP, building testbenches and coverage plans in SystemVerilog/UVM to validate new controller features before tape-out.
Hardware Security Engineer
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/SystemVerilog, collaborating with architects and software teams to meet security and quality standards.