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Spirent Communications
3 weeks ago

Senior Software Engineer

Open 23d North AmericaFull-timeSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Designs and implements a Linux abstraction layer (C/C++) to decouple core software logic from volatile /sys and /etc interfaces, ensuring resilience across OS/kernel upgrades while collaborating with teams on testing, packaging, and future-proofing strategies.

ai ansible api automation bash +12 skills
107 120 – 170 000 $
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TRUST RECRUIT PTE. LTD.
3 weeks ago

Urgent!!! Application Support Analyst (Front-office, E-trading Platform, Linux)

Open 22d APACFull-time
Singapore

Highlights: Permanent job opportunity 5 days work week, normal office working hour Great remuneration & benefits Great career progression With experience in Blomberg / LSEG / Murex / FlexTrade / Calypso / ION are…

aws bash cloud linux perl +1 skills
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Microsoft
3 weeks ago

Principal Subsystem Engineer (Design or DV)

Open 23d On-siteNorth AmericaInternshipPrincipal
United States

Leads hardware subsystem design or verification for Microsoft’s AI SoC (Artificial Intelligence System on Chip) to optimize cloud infrastructure, focusing on high-performance IP, SoC design, and debugging across RTL, synthesis, and post-silicon stages.

agile ai azure cloud cpp +5 skills
188 000 – 304 200 $
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SK Hynix Memory Solution
3 weeks ago

Sr./Staff /Sr. Staff Engineer, IP Design (ASIC)

Open 71d North AmericaStaff
United States

Designs and verifies high-speed interface IP for next-gen storage subsystems (NVMe/Chiplet) in ASICs, leading RTL development through silicon bring-up for enterprise and AI data center storage solutions.

ai cloud machine-learning perl python +2 skills
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Apple
3 weeks ago

Solutions Architect, AppleCare Technologies

Open 23d North America
United States

Design and optimize AppleCare’s support systems and contact-center infrastructure, advising leadership on tech transformations and AI-driven improvements.

agentic-ai ai analytics automation bash +13 skills
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Encora
3 weeks ago

L2 Application Support Engineer

Open 68d LATAMFull-time
Brazil

Job Title: L2 Application Support Engineer Key Skills: Java, C, ETL, Shell script. Location: São Paulo Mode: In-person We at Coforge are hiring L2 Application Support Engineer with the following skill set. Key…

angular automation bash cloud cpp +15 skills
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Microsoft
3 weeks ago

Cloud Network Engineer II

Open 23d On-siteNorth America
United States

Design, automate, and operate secure cloud and hybrid network infrastructure for Microsoft’s global datacenters, focusing on zero-trust and PKI-based trust systems.

analytics ansible automation azure backbone +17 skills
102 100 – 202 200 $
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Astera Labs
3 weeks ago

Manager, Physical Design Engineer

Open 73d On-siteNorth America H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Manages a team of physical design engineers in Toronto to implement high-speed connectivity ASICs for AI infrastructure, using advanced EDA tools and TSMC nodes.

agentic-ai ai automation cad ethernet +4 skills
180 000 – 220 000 CAD
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Astera Labs
3 weeks ago

Principal Physical Design Engineer, STA

Open 73d On-siteNorth AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.

ai automation cloud ethernet networking +6 skills
209 000 – 250 000 $
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Astera Labs
3 weeks ago

Senior ASIC Design Engineer

Open 73d MENASenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.

ai automation ethernet pcie perl +3 skills
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Astera Labs
3 weeks ago

Staff/ Principal Physical Design STA Engineer

Open 73d MENAPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Senior/Staff STA Engineer at Astera Labs in Israel designs and signs off timing for high-performance AI connectivity chips, using EDA tools and SDC constraints to meet aggressive data-center targets.

ai automation ethernet pcie perl +2 skills
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Astera Labs
3 weeks ago

Design Verification Engineer (Intern 2026)

Open 71d North AmericaInternshipIntern H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Design Verification Intern at Astera Labs working on silicon engineering for high-performance compute and networking standards using RTL design languages like Verilog and SystemVerilog.

ai analytics cpp ethernet jtag +5 skills
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Astera Labs
3 weeks ago

Director, Physical Design

Open 65d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Leads a team in Hyderabad to design and implement high-speed connectivity ASICs for AI infrastructure, using advanced EDA tools and flows for full-chip physical design and tapeout.

ai automation cad cloud ethernet +6 skills
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Astera Labs
3 weeks ago

IP Design Director

Open 55d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.

ai authentication ci-cd ethernet pcie +4 skills
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Astera Labs
3 weeks ago

SoC Design Director

Open 55d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.

ai authentication ci-cd ethernet pcie +4 skills
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Astera Labs
3 weeks ago

Staff / Principal ASIC Design Engineer

Open 38d MENAPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.

ai automation ethernet pcie perl +3 skills
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Astera Labs
3 weeks ago

Principal Physical Design Engineer, Methodology

Open 32d On-siteNorth AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Physical Design Engineer defines and maintains reusable RTL-to-GDSII flows and automation for SoC tapeouts, integrating Cadence and Synopsys tools to optimize PPA and schedule predictability.

agentic-ai ai automation cad ci-cd +5 skills
185 000 – 240 000 $
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Cadence Design Systems
3 weeks ago

Principal Design Engineer

Open 15d APACFull-timePrincipal
China

Sr Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities:…

bash ethernet fpga pcie perl +3 skills
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Ambiq Micro, Inc.
3 weeks ago

Sr. Staff Engineer - Digital Design Verification

Open 68d North AmericaStaff
United States

Senior engineer who designs and runs verification tests for low-power System-on-Chip designs used in IoT and edge-AI products, using SystemVerilog, UVM, and C/C++.

ai automation cpp machine-learning perl +3 skills
180 000 – 250 000 $
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Ambiq Micro, Inc.
3 weeks ago

Staff Engineer - Design Verification

Open 53d APACStaff
Singapore

Design verification engineer at Ambiq Micro, Singapore, responsible for verifying low-power SoCs for IoT applications using SystemVerilog/UVM, ARM/RISC-V, and power-aware methodologies.

ai cpp perl python systemverilog +2 skills
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