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ATE Solution Test Engineer
Designs and maintains automated test equipment (ATE) solutions for FPGA chips, focusing on scalable test programs and hardware optimization for production using Teradyne/Advantest platforms.
FIELD APPLICATION ENGINEER - Field-programmable gate array (FPGA)
Supports clients with FPGA-based electronics components, troubleshooting technical issues, training users, and driving new product adoption.
FPGA Engineer: Physical AI & Robotics
Designs FPGA and Adaptive SoC solutions for AI-driven robotics and industrial automation using AMD’s hardware and development tools.
Ingénieur logiciel bas niveau / linux embarqué – Bureau d’études (H/F)
Develops low-level software for embedded Linux systems, including BSP, drivers, and kernel integration, for critical hardware in aerospace, defense, and rail sectors.
VP, Hardware
Lead the strategy, structure, and execution of a multidisciplinary hardware organization for a quantum computing company, integrating photonics, silicon spin qubits, and large-scale technical systems.
Technical Program Manager, Avionics
Leads the full lifecycle of spacecraft avionics hardware from design through flight certification, coordinating engineering, supply chain, manufacturing, and quality teams to meet mission milestones.
Technical Marketing Engineer – FPGA Board and Solution Readiness
Designs, validates, and promotes AMD FPGA and Adaptive SoC evaluation boards and solutions, guiding customers through hardware bring-up, tool workflows, and technical enablement.
Senior Hardware Engineer
Designs and integrates advanced electronic hardware for next-gen combat aircraft, using high-speed digital, FPGA, and AI/ML technologies in a sovereign UK defence project.
FPGA Firmware Engineer
Designs and integrates FPGA firmware for next-gen combat aircraft systems, using VHDL/Verilog and embedded systems while collaborating on cutting-edge defense technology.
Silicon Design Engineer - RTL Integration
Integrates RTL components into AMD's FPGA and programmable SoC products, builds full-chip connectivity models, and verifies architectural intent using Verilog/SystemVerilog and FPGA/SoC design flows.