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Physical Design Technical Lead, ASIC, TPU
Lead the physical design of next-generation AI silicon (TPUs) for Google, driving RTL-to-GDSII implementation, timing/power closure, and cross-functional collaboration to deliver high-performance custom chips.
Sr. RFIC Layout Designer (RFIC Engineering)
Designs and integrates RF and analog layouts for advanced satellite and ground infrastructure chips, ensuring performance and manufacturability while collaborating with cross-functional engineering teams.
RFIC Layout Designer (RFIC Engineering)
Designs and optimizes RF and analog integrated circuit layouts for satellite and ground infrastructure, ensuring performance and manufacturability in advanced nodes.
Sr. RFIC Layout Designer (Starshield Silicon)
Designs and integrates RF and analog layouts for advanced satellite and national security ICs, using EDA tools and scripting to meet space-grade requirements.
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Designs and implements advanced ASIC/SOC chips for SpaceX’s Starlink network, focusing on physical design flows, timing closure, and signoff checks to enable global satellite internet connectivity.
Physical Design Engineer II (Silicon Engineering)
Designs and implements next-generation ASICs for SpaceX's Starlink network, focusing on physical design steps like synthesis, floorplanning, and place-and-route using industry-standard EDA tools.
Physical Design Engineer II (Silicon Engineering)
Designs and implements next-generation ASICs for SpaceX’s Starlink network, focusing on physical design steps like synthesis, floorplanning, and timing closure to enable global satellite internet connectivity.
Software Engineer, Storage Infrastructure
Apple Services Engineering (ASE) designs, builds, and operates the cloud infrastructure, server systems, and platform technologies that power many of Apple's most beloved experiences. Within ASE, the Storage…
Senior Design Verification Engineer
Senior engineer builds and automates hardware verification environments for Microsoft’s cloud silicon, using emulation platforms like Zebu and Palladium to validate SoC designs before manufacturing.
Lead SoC Validation Architect
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Physical Design Leader
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
DFT RTL Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
SoC Power Architect, Pixel Power
Designs and analyzes System on a Chip (SoC) power architectures for Google Pixel devices, benchmarking competitors and driving hardware innovation in mobile consumer electronics.
Staff Engineer - Design Verification
Design Verification Engineer building and owning verification environments for complex SoC power-management chips using UVM, SystemVerilog, and industry-standard tools.
Embedded Software Engineer (cleared)
Develops secure voice software for defense products using C/C++, Rust, and embedded Linux, requiring a U.S. security clearance and U.S. citizenship.
Senior Quality Engineering Manager
Do you want to help build some of the largest and most consequential enterprise and customer technology systems in the world? Join Apple’s Information Systems and Technology (IS&T) organization. IS&T is the…
Senior Specialist, Integration and Test Engineer
L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers’ mission and quest for professional…
IC RTL2GDS Architect, AE
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview The Architect will serve as a technical leader within Cadence’s North America Field Applications…
Design Automation Engineer
Design Automation Engineer develops and maintains static timing analysis (STA) flows and tools for advanced digital design projects using Synopsys PrimeTime and Cadence Tempus, with scripting in Python, Tcl, and Shell.
Application Engineer, RTL2GDS Sr Director
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview The Sr Application Engineer Architect will serve as a senior technical leader within Cadence’s…