American multinational semiconductor company
Principal FPGA engineer in AMD's Network Technology Solutions Group, owning the full lifecycle of control-path FPGAs for high-speed networking products used in AI data centers — from architecture specs and Verilog/SystemVerilog RTL through synthesis, timing closure, and board bring-up with ODM/JDM partners. Onsite in Santa Clara, CA; not eligible for visa sponsorship.
MTS Silicon Design Engineer at AMD's Xilinx subsidiary in San Jose: researches, designs, and verifies ASICs end to end — architecture and logic design, module interfaces, synthesis, place-and-route, timing and power analysis. Core focus areas are high-speed I/O (Ethernet/PCIe), signal/power integrity, and memory systems (DRAM/SSD) in Unix/Linux environments.
Principal-level silicon design engineer at AMD leading the definition, design, verification, and documentation of ASICs — including architecture, logic design, simulation, and physical design (synthesis, place-and-route, timing/power) for CPU/GPU products, on-site in Santa Clara. Requires an MS in EE/CE (or BS plus 7 years) and 5 years of related experience.
Senior Silicon Design Engineer at AMD's Xilinx subsidiary in San Jose: researches, designs, and verifies ASICs — defining architecture and logic design, building timing constraints for IPs/blocks/full-chip, and analyzing timing and RTL quality using EDA tools (Synopsys Design Compiler/PrimeTime, SpyGlass, FishTail) with TCL scripting on Linux.
AMD (via its Xilinx subsidiary) is hiring Sr. Silicon Design Engineers in Austin, TX to define, design, verify, and document ASICs — covering architecture, logic design, simulation, synthesis, place-and-route, timing, and power analysis. Core stack: deep-submicron ASIC physical design, back-end EDA tools, TCL, and Perl.
AMD is hiring an SMTS Silicon Design Engineer in Austin, TX to lead formal verification research for GPU/processor designs — defining long-term formal verification strategy and building methodology and infrastructure (FPV, DPV, SEV) using SystemVerilog Assertions and tools like JasperGold, VC Formal, and Murphi, while contributing to ASIC architecture, logic design, and verification.
Entry-level Silicon Design Engineer at AMD's Xilinx subsidiary in San Jose, defining, designing, verifying, and documenting ASICs — from architecture and logic design to simulation, synthesis, place-and-route, timing and power. Key tech: RTL/Verilog, STA, VCS/Cadence/Mentor Graphics tools, Perl/Python/C++, and FPGA methodologies.
Sr. Silicon Design Engineer at AMD in Austin, TX: research, design, verify, and document ASICs and processors — architecture definition, logic design, simulation, synthesis, place-and-route, timing and power analysis. Requires experience with SOC/CPU architecture, C++ or Python, OpenCL, OOP, and ML accelerator hardware-software co-design.
AMD's Xilinx subsidiary is hiring a Sr. Silicon Design Engineer in San Jose to define, design, verify, and document ASICs — architecture and logic design, RTL coding in Verilog/SystemVerilog, simulation, synthesis, timing and power analysis — using front-end EDA/CAD tools on Linux/Unix with TCL, Perl, Ruby, and Python scripting.
Senior silicon design engineer on AMD's CDFX DV team performing DFT IP verification for CPU/ASIC projects: creating test plans, building scalable verification components and random-constrained stimulus, debugging regressions, closing code coverage, and leading DV execution and tape-out readiness signoff. Can work remotely.
AMD (Xilinx subsidiary) is hiring an MTS Silicon Design Engineer in San Jose to define, design, verify, and debug custom mixed-signal circuits — including clock distribution networks and low-power high-speed digital blocks — spanning architecture, logic design, simulation, ASIC physical design (synthesis, STA), and product bring-up, using C/C++/Python and Unix/Linux.
AMD is hiring Silicon Design Engineers in Austin, TX to research, design, verify, and document ASICs for its CPU/GPU/SoC products — covering architecture and logic design, simulation, synthesis, place-and-route, and timing/power analysis using Verilog/SystemVerilog/VHDL and C/C++/Python. Multiple openings; work is performed under supervision.
AMD is hiring an MTS Silicon Design Engineer in Santa Clara to research, design, and verify ASICs for semiconductor products — leading architecture and logic design, defining module interfaces, running simulation and verification, and optimizing for power, performance, area, and timing. Core tools: SystemVerilog, Python, front-end EDA tools, Unix/Linux, Git.
Senior silicon design engineer at AMD in Santa Clara: research, design, and verify ASICs/semiconductor components — defining architectures, writing RTL, modeling functionality, and handling low-power design and post-silicon debugging using Verilog, SystemVerilog, and VHDL with little supervision.
Senior silicon design engineer at AMD designing analog power-management IP in advanced process nodes: leads ASIC definition, logic design, floorplanning/layout in Cadence Virtuoso, and electromigration/reliability analysis with Ansys Totem and RedHawk, optimizing performance, power, area, and reliability across the design flow.
AMD is hiring a Sr. Silicon Design Engineer in Santa Clara to research, design, verify, and test ASIC/semiconductor components — architecture and logic design, RTL coding, simulation, synthesis, place-and-route, and timing/power analysis. Core tools: Verilog/SystemVerilog/VHDL, TCL/C/C++/Perl, VCS, EDA tools, Unix/Linux.
AMD is hiring a Principal (PMTS) Silicon Design Engineer in Austin, TX to lead ASIC definition, design, verification, and documentation, including CPU competitive analysis and power/droop modeling frameworks. Day-to-day work centers on C/C++/Python scripting, kernel and driver development, validation tooling, and x86/ARM assembly.
Senior Silicon Design Engineer at AMD in Santa Clara: research, design, verify, and document ASICs for semiconductor products — defining architecture/logic design, RTL coding, and running UVM-based functional verification of CPUs/microprocessors using Verilog/SystemVerilog/VHDL, C/C++/Python, and Unix/Linux tooling.
Senior Silicon Design Engineer at AMD in Santa Clara designing and verifying ASICs: architecture and logic design, RTL front-end integration, transitioning RTL to physical design, and evaluating synthesis, place-and-route, timing, and power. Uses Verilog/SystemVerilog/VHDL, SOC/GPU/CPU architecture knowledge, C/C++/Python, and ASIC design tools.
MTS Silicon Design Engineer at AMD researches, designs, verifies, and documents ASICs for semiconductor products — determining architecture and logic design, defining simulation interfaces, and evaluating synthesis, place-and-route, timing, and power with cross-functional teams. Core stack: Verilog/VHDL/SystemVerilog, UVM, TCL, Python, Git, and front-end EDA tools.