American multinational semiconductor company
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Senior program manager on AMD's DPEG Hardware Program Management team, coordinating engineering, sales, manufacturing, and customer teams to deliver next-generation hardware platforms — driving schedules, risks, escalations, and executive status reporting. Onsite in Austin, TX; no visa sponsorship.
Lead BIOS Firmware Architect at AMD developing next-generation UEFI/BIOS for AI and GPU-accelerated server platforms — driving firmware architecture, silicon enablement, platform bring-up, security and RAS features, and mentoring engineers while working with hyperscale customers and ODM/OEM partners. Core tech: UEFI/EDK II, C/C++, PCIe Gen5/6, CXL, ACPI, OpenBMC.
Lead firmware architect at AMD defining the firmware architecture strategy for next-generation AI data center platforms — spanning BIOS, BMC, telemetry, RAS, and platform security for hyperscale AI training and inference. Hands-on leadership across OpenBMC, UEFI, CXL/PCIe fabrics, and embedded Linux, working with silicon, platform, and hyperscale customers.
Senior test engineer at AMD leading semiconductor test strategy: architecting ATE test programs, debug/root-cause methodologies, and automation for first-silicon bring-up and production, while mentoring engineers and driving cross-functional technical decisions. Core tech: Advantest T2000/V93K ATE platforms, C/C++, Python, Java.
Program Manager at AMD's Austin, TX site who coordinates manufacturing change management and Material Review Board (MRB) activities across global semiconductor operations. Day to day, they facilitate cross-functional reviews with Product Engineering, Manufacturing, Quality, and Supply Chain to contain issues, manage material disposition, and drive decisions to closure.
Principal-level role defining the validation strategy for AMD's next-generation data center GPU, AI/ML, and HPC accelerators — architecting validation methodologies, coverage models, automation and emulation frameworks, and leading complex silicon/system debug (coherency, HBM, PCIe, security). Hands-on work with C/C++, Python, and Linux/Windows server environments.
AMD's Embedded team is hiring a Senior Product Line Manager to own the strategy, business, and product line for custom FPGA & Adaptive SoC products, driving adoption across data center, communications, automotive, industrial, and aerospace markets. The role combines technical depth in FPGAs/SoCs and embedded systems with new product introduction, customer engagement, and cross-functional leadershi
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
AMD is hiring a CPU Core RTL Design Engineer in Austin, TX to design and optimize RTL for next-generation high-performance processor cores (load/store, decode, and other core subsystems) across client, server, and AI platforms. The role centers on Verilog/SystemVerilog RTL development, microarchitecture definition, and collaboration with architecture, verification, and physical design teams throug
Senior program manager in AMD's Data Center Platform Engineering Group who qualifies and enables component vendors/suppliers for the Instinct AI and server roadmap — coordinating architects, procurement, quality, and external OEM/ODM partners, leading vendor audits, and managing schedules, risks, and supplier scorecards using tools like Jira, Confluence, and PowerBI.
AMD's Data Center Platform Engineering Group in Secaucus, NJ is hiring a Lead Software Development Engineer to build and validate software for AI rack server platforms — designing scalable architectures that integrate with datacenter hardware (CPUs, GPUs, DPUs, switches), supporting manufacturing and customers, and mentoring junior engineers. Key tech: Python/C/Rust/C++, Docker/Kubernetes/Slurm, L
AMD's SCIO team is hiring a SerDes engineer to own applications, firmware, and validation of next-gen high-speed serial interface IP across electrical and optical domains. Day to day: first-silicon bring-up, PCIe/Ethernet compliance and interop testing, embedded firmware for SerDes/silicon photonics, and building automated characterization and test tooling.
Architect and technical lead for embedded firmware on AMD's data center GPU and AI accelerator platforms (Helios and future products): leading firmware design, development, debugging, validation, and release in C/C++ on Linux toolchains, supporting memory configuration, diagnosing post-silicon issues, and mentoring engineers.