American multinational semiconductor company
Senior software system designer at AMD researching, designing, developing, and testing software and systems for semiconductor products — implementing virtualization and server platform protection features. Core stack: C, C++, Python, Linux/Windows internals, OS kernel development. Remote work allowed; multiple openings.
Senior silicon design engineer on AMD's CDFX DV team performing DFT IP verification for CPU/ASIC projects: creating test plans, building scalable verification components and random-constrained stimulus, debugging regressions, closing code coverage, and leading DV execution and tape-out readiness signoff. Can work remotely.
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Senior silicon design engineer at AMD in Santa Clara: research, design, and verify ASICs/semiconductor components — defining architectures, writing RTL, modeling functionality, and handling low-power design and post-silicon debugging using Verilog, SystemVerilog, and VHDL with little supervision.
Senior silicon design engineer at AMD designing analog power-management IP in advanced process nodes: leads ASIC definition, logic design, floorplanning/layout in Cadence Virtuoso, and electromigration/reliability analysis with Ansys Totem and RedHawk, optimizing performance, power, area, and reliability across the design flow.
AMD is hiring a Sr. Silicon Design Engineer in Santa Clara to research, design, verify, and test ASIC/semiconductor components — architecture and logic design, RTL coding, simulation, synthesis, place-and-route, and timing/power analysis. Core tools: Verilog/SystemVerilog/VHDL, TCL/C/C++/Perl, VCS, EDA tools, Unix/Linux.
Senior software development engineer at AMD researching, designing, developing, and testing systems-level software, compilers, and network distribution software for semiconductor operations. Day-to-day work spans debugging, software verification, and tooling using C/C++, Python, Java/JavaScript, MS SQL Server, Git, and Agile. Multiple openings; can work remotely.
Senior Silicon Design Engineer at AMD in Santa Clara: research, design, verify, and document ASICs for semiconductor products — defining architecture/logic design, RTL coding, and running UVM-based functional verification of CPUs/microprocessors using Verilog/SystemVerilog/VHDL, C/C++/Python, and Unix/Linux tooling.
Senior Silicon Design Engineer at AMD in Santa Clara designing and verifying ASICs: architecture and logic design, RTL front-end integration, transitioning RTL to physical design, and evaluating synthesis, place-and-route, timing, and power. Uses Verilog/SystemVerilog/VHDL, SOC/GPU/CPU architecture knowledge, C/C++/Python, and ASIC design tools.
AMD's Xilinx subsidiary is hiring a Sr. Software Development Engineer in San Jose to research, design, develop, and test OS-level software, compilers, and reference-design platform components for semiconductor products, including C models and functional verification. Core stack: C/C++, Python, Bash/Shell, Linux/Windows internals, DMA, GPIO, and I2C.
Senior Software Development Engineer at AMD's Xilinx subsidiary in San Jose, researching, designing, developing and testing OS-level software, compilers and tools for semiconductor operations. Day-to-day work spans Python/Bash scripting, ML (TensorFlow), REST microservices, Azure data/streaming services, and CI/CD with Azure DevOps.
Senior silicon design engineer at AMD in Santa Clara doing ASIC definition, architecture and logic design, verification, and RTL simulation — including building performance microbenchmarks and debug tools for the Infinity Fabric IP at IP/SoC level. Core stack: Verilog/SystemVerilog/VHDL, Python/Perl/TCL, Unix/Linux.
Sr. Software Development Engineer at AMD (Boxborough, MA) researching, designing, and debugging systems-level software — operating systems, compilers, and network distribution software — supporting semiconductor operations and hardware compatibility. Requires experience with OOP, multi-threading, Linux/macOS/Unix debugging, REST APIs, and distributed systems.
Senior (SMTS) software development engineer at AMD designing, developing, and debugging operating-systems-level software, compilers, and network/cloud tools supporting semiconductor operations. Day-to-day work spans systems-level and platform reliability engineering using C++/Python/Java/Go, Kubernetes GPU clusters, Prometheus/Grafana/Elasticsearch monitoring, CI/CD pipelines, and Terraform.
AMD's Xilinx subsidiary seeks a Sr. Program Manager in San Jose to define, plan, and drive program schedules, resources, risks, and dashboards across engineering teams, collaborating on dependencies and escalations, with required experience in Jira/Confluence, generative AI program management, and AI/ML model development.
AMD is hiring a Sr. Silicon Design Engineer in Orlando, FL to research, design, verify, and document ASICs — covering architecture and logic design, simulation, RTL-to-emulation flows, and SoC bring-up. Core tech: SystemVerilog, front-end EDA tools, C/C++, TCL, Python, Unix/Linux, and Git.
Senior hardware development engineer at AMD (Secaucus, NJ) leading system-level architecture and board-level design for proprietary products: writing specs and BOMs, directing PCB layout, running SI/PI and power simulations, and hands-on system bring-up and debugging. Core focus: power delivery, high-speed interfaces (PCIe Gen4+, DDR4/5, 400GbE, NVMe), and thermal design.