American multinational semiconductor company
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Senior software engineer at AMD's Xilinx subsidiary developing compilers for deep learning workloads on AMD hardware, plus automation scripts for hardware debugging and software validation. Core stack is C++ and Python with PyTorch/TensorFlow, DNN knowledge (CNN, RNN), Git, and Linux/macOS debugging.
AMD is hiring Software Development Engineers (multiple openings) in Washington, DC to research, design, develop, and test operating systems-level software, compilers, and tools supporting semiconductor products. Day-to-day work spans GPU compiler optimization, OS kernel/systems development, and debugging using Python, C/C++, and CUDA.
AMD (via its Xilinx subsidiary) is hiring Sr. Silicon Design Engineers in Austin, TX to define, design, verify, and document ASICs — covering architecture, logic design, simulation, synthesis, place-and-route, timing, and power analysis. Core stack: deep-submicron ASIC physical design, back-end EDA tools, TCL, and Perl.
AMD is hiring a Sr. Software Development Engineer in Austin, TX to research, design, develop, and test systems-level software — operating systems, compilers, and 3D GPU graphics drivers — plus full-stack web apps (React/Node, Flask/Django/FastAPI), Scala/Python streaming data pipelines, dashboards, and CI/CD automation.
AMD is hiring an SMTS Silicon Design Engineer in Austin, TX to lead formal verification research for GPU/processor designs — defining long-term formal verification strategy and building methodology and infrastructure (FPV, DPV, SEV) using SystemVerilog Assertions and tools like JasperGold, VC Formal, and Murphi, while contributing to ASIC architecture, logic design, and verification.
Senior (SMTS) software development engineer at AMD's Xilinx subsidiary, researching, designing, and testing OS-level software, compilers, drivers, and developer tools for semiconductor products — centered on embedded systems, Linux kernel/driver work, and CPU/GPU/SoC and FPGA platforms. Can work remotely; multiple openings.
Entry-level Silicon Design Engineer at AMD's Xilinx subsidiary in San Jose, defining, designing, verifying, and documenting ASICs — from architecture and logic design to simulation, synthesis, place-and-route, timing and power. Key tech: RTL/Verilog, STA, VCS/Cadence/Mentor Graphics tools, Perl/Python/C++, and FPGA methodologies.
MTS-level software engineer at AMD researching, designing, developing, and testing systems-level software — operating systems, compilers, and network distribution software — supporting semiconductor operations. Day-to-day work spans coding, code reviews, unit tests, documentation, and cross-team coordination, mainly in Java/C#/C++ with multithreaded, low-latency systems on Linux and Windows.
Sr. Silicon Design Engineer at AMD in Austin, TX: research, design, verify, and document ASICs and processors — architecture definition, logic design, simulation, synthesis, place-and-route, timing and power analysis. Requires experience with SOC/CPU architecture, C++ or Python, OpenCL, OOP, and ML accelerator hardware-software co-design.
AMD's Xilinx subsidiary is hiring a Sr. Silicon Design Engineer in San Jose to define, design, verify, and document ASICs — architecture and logic design, RTL coding in Verilog/SystemVerilog, simulation, synthesis, timing and power analysis — using front-end EDA/CAD tools on Linux/Unix with TCL, Perl, Ruby, and Python scripting.
Senior software system designer at AMD researching, designing, developing, and testing software and systems for semiconductor products — implementing virtualization and server platform protection features. Core stack: C, C++, Python, Linux/Windows internals, OS kernel development. Remote work allowed; multiple openings.
AMD (Xilinx subsidiary) is hiring an MTS Silicon Design Engineer in San Jose to define, design, verify, and debug custom mixed-signal circuits — including clock distribution networks and low-power high-speed digital blocks — spanning architecture, logic design, simulation, ASIC physical design (synthesis, STA), and product bring-up, using C/C++/Python and Unix/Linux.
AMD is hiring Silicon Design Engineers in Austin, TX to research, design, verify, and document ASICs for its CPU/GPU/SoC products — covering architecture and logic design, simulation, synthesis, place-and-route, and timing/power analysis using Verilog/SystemVerilog/VHDL and C/C++/Python. Multiple openings; work is performed under supervision.
AMD is hiring an MTS Silicon Design Engineer in Santa Clara to research, design, and verify ASICs for semiconductor products — leading architecture and logic design, defining module interfaces, running simulation and verification, and optimizing for power, performance, area, and timing. Core tools: SystemVerilog, Python, front-end EDA tools, Unix/Linux, Git.
Senior silicon design engineer at AMD in Santa Clara: research, design, and verify ASICs/semiconductor components — defining architectures, writing RTL, modeling functionality, and handling low-power design and post-silicon debugging using Verilog, SystemVerilog, and VHDL with little supervision.
Senior silicon design engineer at AMD designing analog power-management IP in advanced process nodes: leads ASIC definition, logic design, floorplanning/layout in Cadence Virtuoso, and electromigration/reliability analysis with Ansys Totem and RedHawk, optimizing performance, power, area, and reliability across the design flow.