American multinational semiconductor company
Performance-focused software engineer at AMD who analyzes application performance on mainstream CPUs, finds and diagnoses bottlenecks using tools and source code, designs optimizations and workarounds, and contributes performance improvements to open source and partner software vendors. Core tech: C/C++, SIMD/AVX512, LLVM, CPU architecture, parallel programming.
AMD is hiring a Sr. Silicon Design Engineer in Santa Clara to research, design, verify, and test ASIC/semiconductor components — architecture and logic design, RTL coding, simulation, synthesis, place-and-route, and timing/power analysis. Core tools: Verilog/SystemVerilog/VHDL, TCL/C/C++/Perl, VCS, EDA tools, Unix/Linux.
Senior software development engineer at AMD researching, designing, developing, and testing systems-level software, compilers, and network distribution software for semiconductor operations. Day-to-day work spans debugging, software verification, and tooling using C/C++, Python, Java/JavaScript, MS SQL Server, Git, and Agile. Multiple openings; can work remotely.
AMD Design, LLC (AMD subsidiary) in Austin, TX is hiring MTS Software Development Engineers to research, design, develop, and test operating systems-level software for next-generation microprocessors, releasing test programs into high-volume manufacturing. Day-to-day involves test planning, pattern debug, silicon characterization, and data analysis using Python, Golang, Linux/Unix, and Git.
AMD is hiring a Principal (PMTS) Silicon Design Engineer in Austin, TX to lead ASIC definition, design, verification, and documentation, including CPU competitive analysis and power/droop modeling frameworks. Day-to-day work centers on C/C++/Python scripting, kernel and driver development, validation tooling, and x86/ARM assembly.
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Expert analog/mixed-signal IC designer on AMD's SerDes Technology Group in San Jose, owning performance-critical blocks in high-speed transceivers — high-speed data converters (DAC/ADC), clocking (PLLs, dividers, buffers), and analog front-ends. Defines Tx/Rx micro-architectures, owns power/performance/area/jitter budgets, mentors engineers, and supports silicon bring-up and validation.
Senior Silicon Design Engineer at AMD in Santa Clara: research, design, verify, and document ASICs for semiconductor products — defining architecture/logic design, RTL coding, and running UVM-based functional verification of CPUs/microprocessors using Verilog/SystemVerilog/VHDL, C/C++/Python, and Unix/Linux tooling.
Senior Silicon Design Engineer at AMD in Santa Clara designing and verifying ASICs: architecture and logic design, RTL front-end integration, transitioning RTL to physical design, and evaluating synthesis, place-and-route, timing, and power. Uses Verilog/SystemVerilog/VHDL, SOC/GPU/CPU architecture knowledge, C/C++/Python, and ASIC design tools.
AMD's Xilinx subsidiary is hiring a Sr. Software Development Engineer in San Jose to research, design, develop, and test OS-level software, compilers, and reference-design platform components for semiconductor products, including C models and functional verification. Core stack: C/C++, Python, Bash/Shell, Linux/Windows internals, DMA, GPIO, and I2C.
MTS Silicon Design Engineer at AMD researches, designs, verifies, and documents ASICs for semiconductor products — determining architecture and logic design, defining simulation interfaces, and evaluating synthesis, place-and-route, timing, and power with cross-functional teams. Core stack: Verilog/VHDL/SystemVerilog, UVM, TCL, Python, Git, and front-end EDA tools.
AMD is hiring an MTS Software Development Engineer in Santa Clara to architect and drive its AI software stack (ROCm) — optimizing performance from GPU kernels to large-scale distributed multi-GPU systems, and using LLM/agent-based tooling to accelerate development for demanding workloads like foundation models and autonomous AI agents.
Senior Software Development Engineer at AMD's Xilinx subsidiary in San Jose, researching, designing, developing and testing OS-level software, compilers and tools for semiconductor operations. Day-to-day work spans Python/Bash scripting, ML (TensorFlow), REST microservices, Azure data/streaming services, and CI/CD with Azure DevOps.
Senior silicon design engineer at AMD in Santa Clara doing ASIC definition, architecture and logic design, verification, and RTL simulation — including building performance microbenchmarks and debug tools for the Infinity Fabric IP at IP/SoC level. Core stack: Verilog/SystemVerilog/VHDL, Python/Perl/TCL, Unix/Linux.
MTS-level Silicon Design Engineer at AMD in Austin, TX: designs, verifies, and documents ASIC development for CPU/GPU products — architecture and logic design, simulation, synthesis, place-and-route, and timing/power closure. Requires a master's degree, 1 year of relevant experience, and tools like Prime Power, STA, and Perl/Tcl/Python scripting.
MTS IT Engineer at AMD in Austin, TX: perform SAP Basis administration — installs, upgrades, patching, monitoring, tuning, and disaster recovery — across SAP S/4HANA, HANA DB, and SAP BTP, while also implementing security controls (firewalls, vulnerability monitoring, incident response) and integrations with tools like Ariba, Concur, and SuccessFactors.
AMD's Xilinx subsidiary is hiring an MTS Silicon Design Engineer in San Jose to research, design, and verify ASICs — owning architecture, RTL design (Verilog/SystemVerilog), synthesis, timing closure, CDC/RDC analysis, and silicon debug while collaborating with verification, DFT, and physical design teams.