American multinational semiconductor company
AMD is hiring Software Development Engineers in Austin, TX to research, design, develop, and test operating systems-level software, compilers, and related tools for semiconductor operations. The role centers on systems-level development and debugging in C, C++, or Python across Unix/Linux environments, with exposure to machine learning.
Senior engineer developing high-performance collective communication libraries (RCCL), GPU communication runtimes, and benchmarking tools for AI/HPC workloads on AMD Instinct GPUs. Day to day: C/C++/Python and CUDA work tuning multi-GPU/multi-node collectives (AllReduce, AllGather, etc.) across PCIe, xGMI, and RDMA networks within the ROCm stack.
Senior IT Engineer at AMD's Xilinx subsidiary in San Jose: designs, builds, and optimizes scalable data pipelines (Kafka, Spark, Flink, Apache Iceberg) and large relational databases/warehouses, monitors performance, applies data governance, and supports AI/ML and business-system workloads.
Senior engineer at AMD in Austin, TX researching, designing, developing, and testing OS-level software, compilers, network distribution software, and next-generation test automation systems for semiconductor operations. Core stack includes Python, JavaScript, Unix/Linux, and web services (REST/XML/JSON).
Senior (SMTS) software development engineer at AMD in Austin, TX working on systems-level GPU software: designing and debugging drivers, compilers, and tools, joining ASIC and hardware bring-ups, and optimizing 3D, compute, ray-tracing, and machine learning pipelines using C/C++/Python and APIs like OpenCL, OpenGL, DirectX, Vulkan, and CUDA.
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AMD (via its Xilinx subsidiary) is hiring an MTS Silicon Design Engineer in San Jose to research, design, and verify ASICs — from architecture and logic design through simulation, synthesis, place-and-route, and timing/power analysis — using RTL, Verilog/VHDL, SystemVerilog/UVM, EDA/CAD tools, and C/C++, TCL, Perl, Python, and Shell scripting.
AMD (Xilinx subsidiary) is hiring Test Engineers in San Jose to develop ATE test programs and data infrastructure for next-gen FPGAs — analyzing volume test data for yield and test-time issues, building dashboards and pipelines, and working on Advantest, Verigy, and Teradyne platforms using Python, C/C++, Ruby, and Verilog/VHDL.
Principal-level software engineer at AMD building and maintaining CI/CD pipelines and platforms (Buildkite, GitHub Actions, Jenkins) for chip development, leading individual contributors, and modernizing developer workflows across component teams. Requires deep C/C++/Perl/Python, Unix/Linux internals, and cloud (AWS/Azure/GCP) experience.
MTS Software Development Engineer at AMD researches, designs, develops, and tests operating-systems-level software, compilers, and tools supporting semiconductor products. Day-to-day work spans kernel/systems development, GPU code optimization, and debugging in C/C++ or Python, plus deep learning frameworks like ONNX, PyTorch, and TensorFlow.
An engineering intern at AMD in Cork will design and verify high-speed SerDes and analog/mixed-signal circuits for next-gen CPUs, GPUs, and FPGAs using Verilog, Python, and industry tools.
Lead/senior FPGA systems design engineer at AMD in Hyderabad: design FPGA-based hardware systems, do RTL coding and system-level simulation, develop applications over HDMI, MIPI, PCIe, Ethernet and SDI, implement optimized algorithms via HLS, and research deep-learning algorithms (CNN, LSTM) on UltraScale+ MPSoC and Versal platforms.
Security engineer in AMD's Product Security Office implementing and validating platform security for AI systems across hardware, firmware, and software — running security assessments, driving vulnerability fixes, provisioning keys/certificates for secure boot and attestation, and building security tooling. Based in San Diego, CA; needs C/C++, Python, Linux, and deep platform-security experience.
Senior Silicon Design Engineer at AMD's AI Group co-designs the hardware-software interface for Instinct GPUs: builds performance/power models, writes GPU kernels and compiler/runtime passes (ROCm, IREE, Linux kernel), and feeds AI workload analysis back into next-gen silicon design. Located in San Jose, CA; no visa sponsorship.
Power and frequency modeling architect on AMD's Central Methodology team: sets power/timing targets and builds decision-grade power-vs-frequency models for AMD's high-performance CPU cores, GPUs, and AI chips from concept through post-silicon production. Works across divisions using Python, Excel, VLSI/digital design, and computer architecture.