AMD
American multinational semiconductor company
Open positions
Lead Hardware Systems Design Engineer
Leads architecture, design, validation, and debug of cloud-scale server platforms and complex PCBs in AMD's Data Center Platform Engineering Group — from schematics and layout through bring-up and production. Core work spans high-speed hardware design (PCIe, DDR, Ethernet, USB, SAS/SATA), signal/power integrity, and cross-team technical leadership.
UEFI / BIOS Firmware Engineer
Develops and deploys platform BIOS/firmware for AMD's EPYC datacenter server processors on the Datacenter Firmware team — designing firmware flows, debugging, and validating across the product lifecycle with silicon and platform teams. Core tech: C, x86 assembly, UEFI/BIOS (AMI AptioV), x86 architecture.
RTL Methodology Silicon Design Engineer
Builds and owns the RTL design methodology, tooling, and AI-powered capabilities for AMD's next-generation CPU core in Austin, TX. Day to day: maintaining linting/static-analysis flows and HDL parsers/AST tooling, and developing LLM-based assistants and agentic workflows to accelerate RTL design, review, and debug.
Technical Program Manager, Thermal & Mechanical Engineering
At AMD in Penang, Malaysia, this Technical Program Manager leads thermal, mechanical and advanced board-assembly (SMT/large BGA) development programs from requirements through qualification, manufacturing release and production ramp, coordinating package, board, cooling and chassis integration across global engineering and supplier teams.
Software Development Manager
Engineering manager role at AMD's Global Cluster Engineering group building an internal AI-agent platform that autonomously runs hardware validation campaigns — day to day spans LLM multi-agent orchestration, RAG pipelines with vector and knowledge-graph retrieval, MCP backend services, and developer tooling, primarily in Python on cloud infrastructure.
Senior Compiler Software Engineer
Join AMD's core team building a machine learning model compiler for AMD AIE hardware in Ryzen AI PCs and embedded FPGA devices. Day to day: compiling ONNX/PyTorch models into optimized code for AIE VLIW arrays, partitioning models across x86/embedded/FPGA/AIE, and building the runtime — using C/C++, Python, and MLIR/LLVM.
Silicon Photonics Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Lead Systems Engineer, Enterprise AI Server Platform Validation
Leads end-to-end validation of AMD's enterprise AI server platforms (EPYC/Instinct): defining validation strategy, driving post-silicon bring-up and debug, and aligning cross-functional teams across architecture, silicon, firmware, BIOS, and software. Onsite in Austin, TX; works with Linux, Windows, and hypervisors (VMware, KVM, Hyper-V).
AI Solution Architect
Architects and builds production-ready AI/ML reference solutions for AMD's AI product portfolio — fine-tuning and deploying ML models (LLMs, agentic AI, RAG) on hardware and cloud, benchmarking on AWS/GCP/Azure, and advising Tier 1 customers. Requires Python, C/C++, ML frameworks, and CI/CD experience. Onsite in San Jose.
Interconnect Micro-Architect and Design Development Lead
Senior technical lead on AMD's Infinity Fabric Architecture and RTL team in Austin, driving development of the coherent on-chip interconnect IP behind AMD CPUs and GPUs. Day to day: translating architecture into RTL implementations, scoping work, resolving cross-component dependencies, and steering complex IP from concept through silicon across globally distributed teams.
Staff Engineer, PLL Design/Integration
Staff design engineer on AMD's AECG Fabric/Clock-PLL team architecting, integrating, and characterizing Phase-Locked Loops and analog/mixed-signal IP (VCOs, LDOs, phase interpolators) for FPGA products on leading-edge process nodes, including layout supervision, lab bring-up, and system-level validation in Vivado.
CPU Cache Architect
Experienced design engineer on AMD's Cores Organization developing next-generation CPU core and cache microarchitecture — building cycle-accurate performance simulators, analyzing workloads, and evaluating improvements via emulation and post-silicon experiments. Key tech: C++, scripting, Verilog/RTL, computer architecture.
Generative AI Engineer, Graphics
AI/ML engineer on AMD's Applied Research team developing, training, and optimizing generative AI models for image generation, diffusion-based learning, and multimodal applications, with scalable training/inference pipelines tuned for AMD GPUs. On-site role; core stack is Python, C++, and ML frameworks like PyTorch.
ASIC Design Engineer, PCIe IP Enablement
At AMD in Markham, ON, this engineer integrates and implements AMD's PCIe subsystem IP into SoCs, owning digital IP from architecture through tape-out. Day-to-day work spans RTL design, synthesis, timing/lint/CDC closure, UPF-based low-power flows, and scripting for flow automation.
CPU Core RTL Design Engineer
Design and optimize RTL for next-generation high-performance CPU cores in AMD's central core RTL team, working on pipeline logic and microarchitecture across client, server, and AI platforms. Core tech: Verilog/SystemVerilog, out-of-order CPU design, timing/power optimization, synthesis, and Python/Tcl scripting.