AMD
American multinational semiconductor company
Open positions
Design Verification Engineer
Design Verification Engineer at AMD's Network Technologies Solutions Group in Markham, ON, leading UVM-based verification of networking silicon (IP, subsystem, SoC) spanning Ethernet, PCIe, DMA, and packet processing. Builds SystemVerilog/UVM testbenches, debugs with VCS/Verdi, and drives performance and coverage closure to signoff.
Lead Systems Engineer, Enterprise AI Server Platform Validation
Leads end-to-end validation of AMD's enterprise AI server platforms (EPYC/Instinct): defining validation strategy, driving post-silicon bring-up and debug, and aligning cross-functional teams across architecture, silicon, firmware, BIOS, and software. Onsite in Austin, TX; works with Linux, Windows, and hypervisors (VMware, KVM, Hyper-V).
Systems Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Silicon Design Engineer
1-year contract at AMD's Central DFX group in Markham: implement and deploy automated Design-for-Test (DFT) flows for complex SOC ASICs (APU, game console, GPU products), run design checks, debug CAD/IP regressions, and build automation with Perl, Python, and TCL, including in-house CAD utilities and AI/ML apps.
Systems Test Validation Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Silicon Design Engineer
Senior silicon design engineer on AMD's Fullchip Floorplan CAD team in Shanghai, owning full-chip physical design methodologies and CAD automation for large-scale SoC designs — from concept through production deployment — using Tcl, Python, and Perl with tools like Cadence Innovus and Synopsys Fusion Compiler/ICC2.
Forward Deployed Engineer, AI and GenAI Inference Optimization
Customer-facing Forward Deployed Engineer optimizing GenAI/LLM inference workloads on AMD Instinct GPUs and data center CPUs: tuning vLLM/SGLang pipelines, writing Triton/HIP/CUDA GPU kernels, profiling bottlenecks, and shipping performance and accuracy improvements to strategic customers. Requires 8+ years' experience with Python, C++, and GPU optimization.
Senior Forward Deployed Engineer, AI and GenAI Inference Optimization
Customer-facing senior engineer on AMD's Forward Deployed team in Riyadh, enabling and optimizing GenAI/LLM inference on AMD Instinct GPUs for strategic customers: tuning vLLM/SGLang pipelines, writing GPU kernels (Triton/HIP), and profiling to hit performance targets. Core stack: Python, C++, ROCm/CUDA.
Senior Graphics Machine Learning Engineer
Senior ML engineer at AMD developing and optimizing machine learning models for graphics, rendering, and visual computing on GPUs, collaborating with the Applied Research and Engineering team. Core tech: Python, C++, ML frameworks, neural networks, real-time 3D graphics pipelines, and GPU-accelerated workloads.
Senior Staff Physical Design Engineer
Own end-to-end physical design of multi-million-gate AMD graphics IP blocks for next-gen AI data center chips — floorplanning, synthesis, CTS, routing, timing closure and signoff on advanced nodes, using tools like Synopsys ICC2/Fusion Compiler, Cadence Innovus, and Mentor Calibre, with Python/TCL flow automation and mentoring. On-site in Vancouver, BC or Markham, ON.
Program Manager, Product Infrastructure Engineering
AMD is hiring a Program Manager in Austin, TX to drive end-to-end product cost attainment from concept through production ramp — forecasting costs, running stakeholder and phase-gate reviews, and leading cross-functional cost-improvement projects during NPI. Requires engineering program management experience with complex SOCs or foundry technologies; not eligible for visa sponsorship.
AI Solution Architect
Architects and builds production-ready AI/ML reference solutions for AMD's AI product portfolio — fine-tuning and deploying ML models (LLMs, agentic AI, RAG) on hardware and cloud, benchmarking on AWS/GCP/Azure, and advising Tier 1 customers. Requires Python, C/C++, ML frameworks, and CI/CD experience. Onsite in San Jose.
Systems Test Validation Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Senior Staff Silicon Design Engineer
An SMTS-level analog circuit design engineer on AMD's Ireland SerDes team, designing and verifying high-speed analog circuits (ADC/DAC, equalizers, clocking, drivers) for 200+Gbps SerDes on advanced CMOS FinFET nodes, supporting connectivity for AMD CPU, GPU, and FPGA products.
Staff Silicon Design Engineer
AMD is hiring a Staff Silicon Design Engineer in Belgrade to define and execute hardware emulation test plans: building emulation testbenches, debugging with design and verification teams, and bringing up standard interfaces. Core technologies include SystemVerilog/Verilog, UVM, C/C++, FPGA flows, and AMBA/PCIe/CXL protocols.
Interconnect Micro-Architect and Design Development Lead
Senior technical lead on AMD's Infinity Fabric Architecture and RTL team in Austin, driving development of the coherent on-chip interconnect IP behind AMD CPUs and GPUs. Day to day: translating architecture into RTL implementations, scoping work, resolving cross-component dependencies, and steering complex IP from concept through silicon across globally distributed teams.
Senior Applications Engineer, AI & HPC
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Staff Engineer, PLL Design/Integration
Staff design engineer on AMD's AECG Fabric/Clock-PLL team architecting, integrating, and characterizing Phase-Locked Loops and analog/mixed-signal IP (VCOs, LDOs, phase interpolators) for FPGA products on leading-edge process nodes, including layout supervision, lab bring-up, and system-level validation in Vivado.
CPU Cache Architect
Experienced design engineer on AMD's Cores Organization developing next-generation CPU core and cache microarchitecture — building cycle-accurate performance simulators, analyzing workloads, and evaluating improvements via emulation and post-silicon experiments. Key tech: C++, scripting, Verilog/RTL, computer architecture.
Generative AI Engineer, Graphics
AI/ML engineer on AMD's Applied Research team developing, training, and optimizing generative AI models for image generation, diffusion-based learning, and multimodal applications, with scalable training/inference pipelines tuned for AMD GPUs. On-site role; core stack is Python, C++, and ML frameworks like PyTorch.