AMD
American multinational semiconductor company
Open positions
Firmware Engineering Manager
Builds and leads a new firmware engineering team for AMD's data center GPUs and machine-intelligence processors — recruiting engineers, setting technical direction for graphics firmware (RLC microcode, SOC debug, power/performance management), and owning delivery from architecture through silicon production. Core tech: C/assembly firmware and SOC debug tooling.
Thermal Mechanical Systems Design Lead
Leads thermal and mechanical design for AMD's server/datacenter platforms, working directly with OEM/ODM customers on thermal simulation, testing, validation, and technical enablement for CPU/GPU systems. Day-to-day involves CFD/CAD work (SolidWorks, Flotherm, Ansys Icepak), air/liquid cooling analysis, and power measurement from component to rack level.
GPU Design Verification Engineer
Design verification engineer on AMD's GPU verification team, driving functional and performance closure on digital design blocks within the Graphics Core IP. Day-to-day work centers on UVM testbenches, coverage plans, test suites, root-cause debugging, plus AI-driven verification automation, using SystemVerilog, Verilog, C/C++ and scripting tools.
Design Verification Engineer
Design Verification Engineer at AMD's Network Technologies Solutions Group in Markham, ON, leading UVM-based verification of networking silicon (IP, subsystem, SoC) spanning Ethernet, PCIe, DMA, and packet processing. Builds SystemVerilog/UVM testbenches, debugs with VCS/Verdi, and drives performance and coverage closure to signoff.
Systems Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Silicon Design Engineer
1-year contract at AMD's Central DFX group in Markham: implement and deploy automated Design-for-Test (DFT) flows for complex SOC ASICs (APU, game console, GPU products), run design checks, debug CAD/IP regressions, and build automation with Perl, Python, and TCL, including in-house CAD utilities and AI/ML apps.
Silicon Design Engineer
Senior silicon design engineer on AMD's Fullchip Floorplan CAD team in Shanghai, owning full-chip physical design methodologies and CAD automation for large-scale SoC designs — from concept through production deployment — using Tcl, Python, and Perl with tools like Cadence Innovus and Synopsys Fusion Compiler/ICC2.
Senior Staff Physical Design Engineer
Own end-to-end physical design of multi-million-gate AMD graphics IP blocks for next-gen AI data center chips — floorplanning, synthesis, CTS, routing, timing closure and signoff on advanced nodes, using tools like Synopsys ICC2/Fusion Compiler, Cadence Innovus, and Mentor Calibre, with Python/TCL flow automation and mentoring. On-site in Vancouver, BC or Markham, ON.
ASIC Design Engineer, PCIe IP Enablement
At AMD in Markham, ON, this engineer integrates and implements AMD's PCIe subsystem IP into SoCs, owning digital IP from architecture through tape-out. Day-to-day work spans RTL design, synthesis, timing/lint/CDC closure, UPF-based low-power flows, and scripting for flow automation.
RTL Design Engineer
Designs block-level RTL and integrates embedded microprocessor subsystems and hardware accelerators (security, cryptography, compression, DMA, power management) on AMD's Security IP team, supporting client, server, graphics, and gaming SoCs. Daily work centers on Verilog/SystemVerilog design, debugging regressions, and ASIC signoff flows.
Staff Silicon Design Engineer, Physical Design
Staff engineer on AMD's Singapore silicon design team owning PnR, STA and physical design integration from design handoff through timing convergence, verification and signoff. Work combines EDA tools (Fusion Compiler, Innovus, PrimeTime, Calibre) with Tcl/Python/Perl automation and AI-assisted, agentic workflows.
Silicon Design Engineer
Silicon Design Engineer on AMD's FPGA Product Development Silicon Integration team in Singapore, integrating RTL components into next-generation FPGA and programmable SoC products — building full-chip RTL connectivity models, verifying them against architectural intent, and developing internal tooling. Core stack: Verilog/SystemVerilog, SoC/ASIC design flows, and CAD tools like VCS, Verdi, and Pri