AMD
American multinational semiconductor company
Open positions
Firmware Engineering Manager
Builds and leads a new firmware engineering team for AMD's data center GPUs and machine-intelligence processors — recruiting engineers, setting technical direction for graphics firmware (RLC microcode, SOC debug, power/performance management), and owning delivery from architecture through silicon production. Core tech: C/assembly firmware and SOC debug tooling.
RTL Methodology Silicon Design Engineer
Builds and owns the RTL design methodology, tooling, and AI-powered capabilities for AMD's next-generation CPU core in Austin, TX. Day to day: maintaining linting/static-analysis flows and HDL parsers/AST tooling, and developing LLM-based assistants and agentic workflows to accelerate RTL design, review, and debug.
Technical Program Manager, Thermal & Mechanical Engineering
At AMD in Penang, Malaysia, this Technical Program Manager leads thermal, mechanical and advanced board-assembly (SMT/large BGA) development programs from requirements through qualification, manufacturing release and production ramp, coordinating package, board, cooling and chassis integration across global engineering and supplier teams.
Software Development Manager
Engineering manager role at AMD's Global Cluster Engineering group building an internal AI-agent platform that autonomously runs hardware validation campaigns — day to day spans LLM multi-agent orchestration, RAG pipelines with vector and knowledge-graph retrieval, MCP backend services, and developer tooling, primarily in Python on cloud infrastructure.
Senior Firmware Engineer
Senior firmware engineer on AMD's ICT Firmware Engineering Team (Belgrade or Nis, Serbia, onsite, 12-month fixed-term contract with possible extension). Develops low-level embedded firmware for interconnect technologies like PCIe, CXL, and USB4 in an RTOS environment, from pre-silicon validation through post-silicon and production support. Core stack: C, C++/Python, Zephyr RTOS, Linux.
GPU Design Verification Engineer
Design verification engineer on AMD's GPU verification team, driving functional and performance closure on digital design blocks within the Graphics Core IP. Day-to-day work centers on UVM testbenches, coverage plans, test suites, root-cause debugging, plus AI-driven verification automation, using SystemVerilog, Verilog, C/C++ and scripting tools.
Senior Compiler Software Engineer
Join AMD's core team building a machine learning model compiler for AMD AIE hardware in Ryzen AI PCs and embedded FPGA devices. Day to day: compiling ONNX/PyTorch models into optimized code for AIE VLIW arrays, partitioning models across x86/embedded/FPGA/AIE, and building the runtime — using C/C++, Python, and MLIR/LLVM.
Silicon Photonics Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
AI Engineer
Early-career AI Engineer at AMD's Singapore AI Engineering team building Agentic AI and 'Digital Workers': designing LLM-powered agents with prompt/context engineering and RAG pipelines, then deploying them into real enterprise workflows using Python, agent frameworks, and cloud tooling.
Design Verification Engineer
Design Verification Engineer at AMD's Network Technologies Solutions Group in Markham, ON, leading UVM-based verification of networking silicon (IP, subsystem, SoC) spanning Ethernet, PCIe, DMA, and packet processing. Builds SystemVerilog/UVM testbenches, debugs with VCS/Verdi, and drives performance and coverage closure to signoff.
Systems Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Silicon Design Engineer
1-year contract at AMD's Central DFX group in Markham: implement and deploy automated Design-for-Test (DFT) flows for complex SOC ASICs (APU, game console, GPU products), run design checks, debug CAD/IP regressions, and build automation with Perl, Python, and TCL, including in-house CAD utilities and AI/ML apps.
Silicon Design Engineer
Senior silicon design engineer on AMD's Fullchip Floorplan CAD team in Shanghai, owning full-chip physical design methodologies and CAD automation for large-scale SoC designs — from concept through production deployment — using Tcl, Python, and Perl with tools like Cadence Innovus and Synopsys Fusion Compiler/ICC2.
Forward Deployed Engineer, AI and GenAI Inference Optimization
Customer-facing Forward Deployed Engineer optimizing GenAI/LLM inference workloads on AMD Instinct GPUs and data center CPUs: tuning vLLM/SGLang pipelines, writing Triton/HIP/CUDA GPU kernels, profiling bottlenecks, and shipping performance and accuracy improvements to strategic customers. Requires 8+ years' experience with Python, C++, and GPU optimization.
Senior Forward Deployed Engineer, AI and GenAI Inference Optimization
Customer-facing senior engineer on AMD's Forward Deployed team in Riyadh, enabling and optimizing GenAI/LLM inference on AMD Instinct GPUs for strategic customers: tuning vLLM/SGLang pipelines, writing GPU kernels (Triton/HIP), and profiling to hit performance targets. Core stack: Python, C++, ROCm/CUDA.
Senior Graphics Machine Learning Engineer
Senior ML engineer at AMD developing and optimizing machine learning models for graphics, rendering, and visual computing on GPUs, collaborating with the Applied Research and Engineering team. Core tech: Python, C++, ML frameworks, neural networks, real-time 3D graphics pipelines, and GPU-accelerated workloads.
Senior Staff Physical Design Engineer
Own end-to-end physical design of multi-million-gate AMD graphics IP blocks for next-gen AI data center chips — floorplanning, synthesis, CTS, routing, timing closure and signoff on advanced nodes, using tools like Synopsys ICC2/Fusion Compiler, Cadence Innovus, and Mentor Calibre, with Python/TCL flow automation and mentoring. On-site in Vancouver, BC or Markham, ON.
AI Solution Architect
Architects and builds production-ready AI/ML reference solutions for AMD's AI product portfolio — fine-tuning and deploying ML models (LLMs, agentic AI, RAG) on hardware and cloud, benchmarking on AWS/GCP/Azure, and advising Tier 1 customers. Requires Python, C/C++, ML frameworks, and CI/CD experience. Onsite in San Jose.
Generative AI Engineer, Graphics
AI/ML engineer on AMD's Applied Research team developing, training, and optimizing generative AI models for image generation, diffusion-based learning, and multimodal applications, with scalable training/inference pipelines tuned for AMD GPUs. On-site role; core stack is Python, C++, and ML frameworks like PyTorch.
CPU Core RTL Design Engineer
Design and optimize RTL for next-generation high-performance CPU cores in AMD's central core RTL team, working on pipeline logic and microarchitecture across client, server, and AI platforms. Core tech: Verilog/SystemVerilog, out-of-order CPU design, timing/power optimization, synthesis, and Python/Tcl scripting.