HCLGUVI
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VLSI Design and Verification Mentor
Open 46d APAC
Vietnam
Ho Chi Minh City, Da NangMentor role at HCL GUVI (an edtech/training company) guiding engineers in VLSI: ASIC front-end design and verification (RTL in Verilog/SystemVerilog, UVM testbenches, Synopsys tools, Perl/Python scripting) and physical design flow (floorplanning, timing closure with Cadence Innovus/Synopsys ICC2). Based in Ho Chi Minh City or Da Nang, remote-friendly.
Asic FPGA Perl Prototyping Python +4 skills
30K – 40K INR