Microchip Technology

Iso 9001 Process Improvement

Quality Engineer

Open 29d APACFull-time

Philippines

Engineer II-Quality Location: Philippines - Mphil 1 Time Type: Full time Job Description Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the…

Open 29d HybridEuropeFull-timePrincipal

Principal Design Engineer - Emulation

Germany

Principal Design Engineer- Emulation (m/w/d) Location: Germany - Karlsruhe Time Type: Full time Job Description Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member…

Automation Bash Embedded Linux Firmware FPGA +12 skills

Software Development Engineer

Open 29d APACFull-time

Agile Angular Automation Eclipse Git +8 skills

Develops and maintains Java-based software and web apps using React/Angular, Node.js, and TDD in an Agile environment for Microchip’s embedded-dev tooling.

Open 29d North AmericaInternshipIntern

Intern, Firmware Development

Agile C C++ C# Firmware +4 skills

Intern developing firmware in C for ROC processors, debugging embedded systems, and collaborating on storage solutions for enterprise/data-center environments.

Open 29d North AmericaFull-time

Product Line Manager

Manager-Product Line Location: AZ - Chandler, CA - San Jose - 3870 N. First St, CA - San Jose - Fortune Dr (Micrel HDQ), CA - San Jose - 3850 N. First St Time Type: Full time Job Description Are you looking for a…

Go-to-Market

Open 29d North AmericaFull-timeSenior

Senior Validation Engineer (Systems)

AI Cloud C++ Embedded Software Firmware +12 skills

Sr Engineer I - Validation (Systems) Location: CA - Roseville Time Type: Full time Job Description Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works…

Open 29d APACFull-timePrincipal

Principal Firmware Engineer

Automation CI/CD C++ Firmware Git +7 skills

Principal Engineer designing and optimizing Linux/Windows storage drivers for enterprise SoC devices, collaborating with hardware and QA teams to deliver high-performance, reliable solutions.

Software Engineer

Open 31d APAC

Agile AJAX API Authentication CSS +16 skills

Builds and maintains PHP-based web apps with React frontends and REST APIs for Microchip’s timing/synchronization products, using MySQL/PostgreSQL and Git in an Agile team.

Open 31d North AmericaPrincipal

Ingénieur principal en analogique/ Principal Engineer - Analog Design

Canada

Design, simulate, and validate high-speed analog and mixed-signal IP blocks (PLLs, ADCs, DACs, I/O interfaces) for SoC timing products using Cadence tools and Verilog-A.

Automation Perl Python Tcl Verilog

Open 31d North AmericaPrincipal

Principal DSP Firmware Engineer

Canada

Principal firmware engineer designing DSP algorithms and embedded C/C++ code for ultra-low-jitter timing SoCs used in 5G, IoT, and autonomous vehicles.

Accessibility Agile Confluence C++ Embedded Software +8 skills

107K – 157K $

Open 31d North AmericaPrincipal

Principal Engineer - Design

Automation Bash Embedded Linux Firmware FPGA +12 skills

Principal Design Engineer at Microchip Technology leading hardware/firmware co-development and pre/post-silicon verification using emulators and FPGA platforms for SoC devices.

75K – 232K $

Senior Software Engineer II

Open 33d APACSenior

API CI/CD CMake C++ Docker +10 skills

Build backend services and APIs in Rust/C++ for USB and PCIe/USB Ethernet controller tools, focusing on performance, reliability, and CI/CD integration.

Open 32d APAC, CIS, North AmericaStaff

Technical Staff Engineer - Design

Designs IO pad rings, bump patterns, and connectivity for advanced SoC storage/memory controllers using EDA tools and scripting.

Automation Jira JTAG Machine Learning PCIe +5 skills

Open 32d LATAMFull-timePrincipal

Principal Engineer - Digital Design

Colombia

Principal Digital Design Engineer designing secure embedded controllers and cryptographic hardware for automotive, industrial, and defense markets using ASIC/FPGA flows, Verilog/VHDL, and security countermeasures.

Asic Atlassian Automation Bash Confluence +11 skills

75K – 232K $

Open 32d North AmericaPrincipal

Principal Engineer - Analog Design

Canada

Designs and validates high-speed analog and mixed-signal IP blocks (PLLs, ADCs, DACs, filters) for multi-GHz timing products using Cadence tools and Verilog-A modeling.

Accessibility Automation Perl Python Tcl +1 skills

107K – 157K $

Asic Ethernet FPGA I2c Perl +5 skills

Technical Staff Engineer-Design

Open 37d EuropeStaff

Germany

Designs low-power wireless System-on-Chip solutions, writing RTL code and guiding the SoC through synthesis, timing analysis, and tape-out while collaborating with global teams.

Principal Engineer - Design for Test

Open 39d APACPrincipal

Principal Engineer designs and improves test hardware for microchips, using ATPG, MBIST, and Tessent/Modus tools to enhance coverage and debug silicon issues.

JTAG

Senior Engineer I Design

Open 39d APACSenior

Design-for-Test engineer responsible for inserting boundary scan, memory BIST, and scan logic into complex SoCs, running ATPG, and debugging silicon bring-up on ATE.

Perl Python Tcl