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Design and build confidential AI systems that protect models and data using trusted execution environments, remote attestation, and secure provisioning in cloud-native and on-prem deployments.
Design and validate next-gen accelerator boards for AI/ML/HPC using Openchip silicon, from schematic to production, collaborating with cross-functional teams and suppliers.
Designs high-performance, power-efficient CPU cores for next-gen SoCs, focusing on out-of-order superscalar architectures and multi-core coherency.
Leads the design of high-performance, power-efficient out-of-order superscalar CPU cores for next-gen SoCs, collaborating with teams to optimize performance and integration.
Senior engineer responsible for RTL-to-GDSII physical design of complex digital blocks, including high-speed interfaces and automotive modules, using advanced EDA tools and timing closure techniques.
Senior Offensive Security Engineer at Openchip in Barcelona designs and tests secure RISC-V chip software/firmware, using offensive techniques to find vulnerabilities and align with security standards like FIPS 140-3 and NIST SP 800-193.
Designs and integrates secure hardware I/O solutions and SoC features for high-performance systems, focusing on security, interfaces like PCIe/UCIe, and RISC-V chiplets in Barcelona.
Designs high-performance, power-efficient System-on-Chip (SoC) hardware architectures with a focus on Reliability, Availability, and Serviceability (RAS) features, integrating processing units, memory, and accelerators.
Develops and maintains security features for RISC-V and other hardware platforms, including secure boot and confidential computing, while collaborating with firmware, OS, and middleware teams in Barcelona.
Develop low-level firmware (BIOS, device drivers) and mid-level software (emulation, virtualization) for novel hardware, primarily using C/Rust and Linux kernel internals.
Develop low-level firmware (BIOS, device drivers) and mid-level software (emulation, virtualization) for novel hardware, primarily in C/Rust, to expose hardware features and accelerators in Linux-based systems.
Designs and optimizes high-performance on-chip interconnects for advanced SoCs using RISC-V and UCIe, focusing on memory interfaces, coherency protocols, and power/performance trade-offs.
Senior Validation Engineer in Gdańsk designs and implements test cases and frameworks to validate software components, ensuring high-quality releases while collaborating across teams and integrating testing into the development lifecycle.
Senior DevOps Engineer designs and maintains hybrid infrastructure, CI/CD pipelines, and cloud-native systems in Gdańsk, Poland, using Linux, Kubernetes, Terraform, and Python/Go.
Junior Performance Software Engineer optimizes AI/HPC workloads and benchmarks for RISC-V chips with vector extensions, profiling and tuning performance across simulators, FPGAs, and silicon environments.
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