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50 jobs
ovt
2 views 2 years ago

(Sr.) ISP RTL Design Manager

Open 69d APACSenior
Singapore

Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements,…

Cmos C++ Rtl Signal Processing SystemVerilog +1 skills
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ovt
2 views 2 years ago

Application Engineer: Senior Staff Engineer / Staff Engineer / Senior Engineer

Open 69d APACStaff
Japan

Responsibilities: As an Application engineer for CIS, you will be responsible to: Conduct analytic studies of fundamental performance issues for CIS or ISP and provide technical suggestions of improvement Support…

Cmos C++ C# MATLAB Python +1 skills
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ovt
4 views 2 years ago

(Sr./Staff) Design Verification Engineer

Open 69d APACStaff
Singapore

Description: As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in…

Analytics C++ Uvm
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ovt
5 views 2 years ago

(Sr./Staff) ISP RTL Design Engineer

Open 69d APACStaff
Singapore

Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements,…

Cmos C++ Signal Processing SystemVerilog Verilog
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ovt
4 views 2 years ago

(Sr./Staff) SoC Design Engineer

Open 69d APACStaff
Singapore

Description: You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing engines, neural processing units, advanced video analytics accelerators, and the entire Camera…

Analytics Assembly Bash Perl Python +5 skills
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ovt
5 views 2 years ago

Test engineer: Staff / Senior Engineer / Engineer

Open 69d APACStaff
Japan

Responsibilities: As Test engineer, Collect, verify and analysis mature CIS product of CP testing and trouble shooting program and prepare the NPI device mass production ramp up. ・Develop CIS (CMOS Image Sensor) test…

Cmos C++
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ovt
3 views 3 years ago

(Sr. Staff / Staff Engineer) Design Characterization Engineer

Open 69d APACStaff
Japan

Responsibilities: Execute characterization, measurements, debug, analysis for CMOS image sensors Provide design characterization report, presentation, technical information in timely manner Provide technical solutions…

Cmos
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ovt
3 views 3 years ago

(Sr. Staff / Staff Engineer) Pixel Design Engineer

Open 69d APACStaff
Japan

Responsibilities: Pixel circuit and photodiode design as discussing with process integration group, modeling group, characterization group and peripheral circuit group. Achieve best pixel performance with optimization…
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ovt
3 views 3 years ago

(Sr. Staff / Staff Engineer) Process Integration Engineer

Open 69d APACStaff
Japan

Responsibilities: Develop advanced CIS technologies and lead project through detailed process and process integration knowledge. Complete the project from NTO to risk mass production phase to meet all PRD targets and…
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ovt
4 views 3 years ago

Digital Design engineer: Senior staff engineer / Staff engineer

Open 53d APACStaff
Japan

Responsibilities: Responsible for RTL design and verification using Verilog and System Verilog Define System Architecture and/or Block level Micro Architecture based on product features and performance requirements,…

Cmos Rtl Signal Processing Verilog
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