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3 months ago
Senior/Principal ASIC/RTL Design Engineer
APACPrincipal
India
Role : Senior/Principal ASIC RTL Design Engineer (SoC/Subsystem): Role : Own end-to-end micro-architecture and ASIC RTL design for complex SoCs or large subsystems, from specification through tapeout and silicon…
FPGA PCIe Python Rtl SystemVerilog +2 skills