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2027年研發替代役(數位IC設計工程師)
APAC
Taiwan
Zhubei City, Hsinchu County1.數位電路設計 2.FPGA /ASIC流程.
FPGA
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Multimedia SoC IC數位電路設計 資深工程師/主管
APACSenior
Taiwan
Zhubei City, Hsinchu County1. Design system architecture. 2. Design custom IPs in Verilog according to the system specification. 3. Integrate CPU, ISP, Video CODECs and others peripherals for both FPGA and ASIC. 4. Perform the validation of chip…
Firmware FPGA Verilog