松翰科技股份有限公司
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Design Flow CAD工程師
APAC
Taiwan
Zhubei City, Hsinchu County‧ Familiar with scripting/programming language (TCL / C shell / Perl / Python/ …) ‧ Familiar with IC design flow ‧ Familiar with Verilog & Library characterization ‧ Familiar with EDA tool including Cadence Genus /…
Bash Perl Python Tcl Verilog
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Multimedia SoC IC數位電路設計 資深工程師/主管
APACSenior
Taiwan
Zhubei City, Hsinchu County1. Design system architecture. 2. Design custom IPs in Verilog according to the system specification. 3. Integrate CPU, ISP, Video CODECs and others peripherals for both FPGA and ASIC. 4. Perform the validation of chip…
Firmware FPGA Verilog