SyoSil ApS
1 job
last week
ASIC/FPGA Design and Verification Engineer
Europe
Denmark
SyoSil is hiring ASIC/FPGA design and verification engineers to work on RF radio ASIC projects using SystemVerilog and UVM. The role involves full-cycle IP block development, from architecture to verification, within a collaborative, SCRUM-based international team.
asic cpp firmware fpga linux +8 skills