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RTL Design Engineer
Open 17d
An RTL Design Engineer defines, designs, and integrates RTL for a 5G/6G baseband subsystem made of DSP cores, hardware accelerators, DMA engines, and on-chip interconnects. Day-to-day work spans Verilog/VHDL datapath design, AXI/AHB/APB integration, PPA optimization, and Synopsys/Cadence front-end flows.
Git Perl Python Rtl Tcl +3 skills