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TYLsemi

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42 jobs
TYLsemi
7 views 5 months ago

Staff - Mixed-Signal Design RTL Design Engineer

Open 33d RemoteAPACStaff
India

What You’ll Do Architect , and implement digital PID / cascade control loops (voltage-mode, current-mode, or hybrid) for high-frequency multi-phase IVRs operating at 10–100 MHz. D esign production-quality RTL (Verilog…

AI HPC MATLAB Quantization Simulink +2 skills
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TYLsemi
3 views 6 months ago

Design Verification Architect

Open 22d APAC
India

Role Overview We are seeking a highly experienced Design Verification Architect to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targeting…

Agentic AI AI Anomaly Detection Automation Ethernet +7 skills
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