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硬體/FPGA工程師(工作地點：台南市)
APAC
Taiwan
Central and Western District, Tainan City1. FPGA設計： 1.1 Coding: VHDL, Verilog 1.2 Simulation: Mentor ModelSim, Cadence IES simulator 1.3 Implementation: Xilinx ISE/Vivado, Altera Quartus II 1.4 具IC設計經驗者尤佳 2. 硬體電路設計： 2.1 ARM or Power PC based embedded…
Ethernet Verilog VHDL VoIP
1 views 2 weeks ago
硬體/FPGA工程師(工作地點：台北內湖)
APAC
Taiwan
Neihu District, Taipei City對ASIC/FPGA High Density, Ethernet, SDH/SONET, OrCAD, PADS, Xilinx, Scope, MPLS, MPLS-TP, Logic/Spectrum Analyzer等通訊產品有興趣且具研發創新能力者。
Ethernet FPGA MPLS
3 views 2 weeks ago
資深硬體工程師/主任/副理(工作地點：台北內湖)
APACSenior
Taiwan
Neihu District, Taipei City對ASIC/FPGA High Density, Ethernet, SDH/SONET, OrCAD, PADS, Xilinx, Scope, MPLS, MPLS-TP, Logic/Spectrum Analyzer等通訊產品有興趣且具研發創新能力者。
Ethernet FPGA MPLS