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數位IC設計_工程師/資深工程師(A)_台北
APACSenior
Taiwan
Neihu District, Taipei CityASIC相關產品設計 工作內容： Architecture block definition RTL design and functional verification FPGA verification Synthesis and static timing analysis
FPGA Rtl
2 views 2 months ago
數位IC設計_工程師/資深工程師(B)_台北
APACSenior
Taiwan
Neihu District, Taipei City Display port IP architecture definition RTL design and functional verification FPGA verification Synthesis and static timing analysis
FPGA Rtl
1 views 2 months ago
數位IC 設計_主管 _台北
APAC
Taiwan
Neihu District, Taipei City負責 Display Port IP 規劃與設計 工作內容: Display port IP leader Display port IP architecture definition RTL design and functional verification FPGA verification Synthesis and static timing analysis
FPGA Rtl