Advanced CPO Packaging Technology Development & Integration Manager/Engineer

1. Advanced Packaging Technology Development. Lead the feasibility assessment and development of Co-Packaged Optics (CPO) and advanced wafer-level/panel-level packaging technologies, including 2.5D, 3D, 3.5D integration, EMIB, Fan-Out, and other heterogeneous integration solutions.
2. New Product Introduction (NPI) and Manufacturing Yield Enhancement. Drive NPI activities from engineering builds to production ramp-up, including process planning, DOE development, yield analysis, root-cause investigation, and manufacturing yield improvement.
3. Packaging Solution Development. Develop and implement packaging solutions for Co-Packaged Optics (CPO), optical modules, and advanced logic-memory integration platforms, including HBM and LPDDR technologies.
4. Technology and Supply Chain Management. Collaborate with foundries, OSAT providers, optical component suppliers, module manufacturers, and substrate vendors to evaluate technology capabilities, conduct technical assessments, support cost analysis, and oversee manufacturing readiness.
5. Cross-Functional Project Leadership. Work closely with IC design, package design, testing, quality, and reliability teams to ensure technical requirements, project milestones, and product performance targets are successfully achieved.

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1. Education:

• Master's or Ph.D. degree in Electrical Engineering, Electronics Engineering, Materials Science, Physics, Chemistry, Mechanical Engineering, or a related engineering discipline.

2. Experience:

• 6+ years of experience in semiconductor packaging R&D, process integration, New Product Introduction (NPI), or technology management.
• Experience in optical component/module assembly and testing, 2.5D/3D packaging technologies, or HBM development is highly preferred.

3. Qualifications

• Strong knowledge of packaging processes, material characteristics, and cost structures, including optical component and module assembly/testing, Bumping, Fan-Out, WLCSP, CoWoS, EMIB, and Flip-Chip technologies.
• Proficient in Design of Experiments (DOE), Failure Analysis (FA), and Tape-out processes.
• Familiar with optical component and module design/testing, or logic and memory (DRAM/HBM) integration architectures.
• Possesses a fundamental understanding of Signal Integrity (SI) and Power Integrity (PI), with knowledge of package reliability and common failure mechanisms, and the ability to effectively collaborate with failure analysis and engineering teams.