AI/Deep learning Accelerator - Digital Design Engineer

We are seeking an experienced Digital Design Engineer to drive the architecture and implementation of Andes Deep Learning Accelerator (AnDLA) projects. In this role, you will lead the design of robust memory subsystem architectures and ensure seamless system-level integration across complex modules.

If you are a hardware architect who enjoys the intersection of high-performance memory subsystem design, system bottleneck analysis, and low-power optimization, this is the role for you.

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Responsibilities
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• Memory Subsystem Architecture: Design and implement robust memory subsystem architectures for advanced SoC projects.
• SoC Integration: Perform comprehensive SoC integration and ensure seamless module-to-module communications across complex systems.