AI Design Verification Engineer

1. Verification environment development for AI-processor and peripheral IP design
2. Function verification from IP-level to system level
3. Develop test pattern for power / performance analysis
4. post-sillicon debug
5. emulator environment build up

Requirements

1. familiar with UVM verification methodology and flow
2. familiar with AMBA bus and peripheral controller (ex. DMA )
3. Familiar with with SOC integration and verification flow. FPGA is a plus.
4. Familiar with Perl, C, Verilog, System Verilog
Education: Master's Degree