Analog Design Architect

onsemi is seeking an Analog Design Architect with a strong architecture and technical strategy focus to join its Core Analog IP Development Centre of Excellence in Cork, Ireland. You will shape the architecture, strategy and development roadmaps for power, clock, monitoring and reset IP for the Treo platform in BCD65 technology, including bandgap references, LDOs, DC–DC regulators, oscillators and PLLs.

Your primary focus will be translating product-line needs and longer-term platform requirements into coherent IP architectures, reusable specifications and prioritised roadmaps. You will align stakeholders on technical direction, assess architectural trade-offs and guide engineering teams through implementation, validation and production readiness. Strong circuit-design expertise remains essential: you will contribute selectively to critical circuit development, feasibility studies and complex technical problem-solving rather than routinely owning every stage of block-level implementation. You will also mentor junior engineers and help ensure IP can be integrated and reused across the platform.

IP Architecture, Strategy and Roadmaps

• Define and evolve the architecture and technical strategy for power, clock, monitoring and reset IP in the Treo BCD65 platform, establishing a coherent direction across the IP portfolio.
• Engage directly with product-line teams and stakeholders to understand product needs, operating conditions, integration constraints and future requirements.
• Own the translation of product and platform needs into IP architecture requirements, clear specifications and prioritised, multi-generation development roadmaps for the Core Analog teams, balancing immediate commitments with longer-term capability needs, dependencies and reuse opportunities.
• Lead architectural trade-off studies across performance, power, area, robustness, testability and integration complexity, using circuit-level feasibility analysis where needed to underpin strategic decisions.
• Champion reusable IP, configurable features and consistent interfaces that support adoption across multiple products while limiting unnecessary customisation.
• Build stakeholder alignment on architecture proposals, roadmap priorities and technical investment choices through reviews, presentations and written documentation; revisit priorities as product requirements and platform needs evolve.

Design Guidance and Production Delivery

• Provide architectural direction and technical guidance for analog IP including bandgap references, low-dropout regulators (LDOs), DC–DC regulators, oscillators, phase-locked loops (PLLs), monitoring circuits and reset functions.
• Guide block development from specification through transistor-level design, simulation, layout, verification and silicon characterisation, maintaining alignment with the agreed architecture and contributing hands-on to selected high-risk or novel circuits.
• Define verification expectations and review evidence of performance across process, voltage and temperature corners, including mismatch, noise, stability, start-up behaviour and relevant operating modes.
• Partner with design and layout engineers to establish constraints for matching, parasitics, isolation, coupling and device reliability, and review post-layout results against specifications.
• Collaborate with product integration, validation, test and product engineering teams to resolve issues and support successful transfer to mass production.
• Define and review architecture documentation, integration guidance and characterisation reports that enable efficient IP reuse and maintenance, feeding silicon learnings back into future architectures and roadmaps.

Technical Leadership, Mentoring and AI Adoption

• Mentor junior engineers in analog design fundamentals, simulation methodology, design reviews and silicon debug.
• Lead architecture and design reviews, guide technical decisions and share knowledge to strengthen architectural thinking and engineering practices across the Core Analog teams.
• Help identify and assess practical opportunities for AI-assisted analog design and layout, including design-space exploration, simulation automation, results analysis, documentation and layout assistance.
• Apply sound engineering judgement when evaluating AI-generated outputs, retaining rigorous verification, traceability and protection of confidential design information.

• A bachelor’s degree in electrical or electronic engineering, or a closely related discipline, with at least 15 years of relevant analog IC design experience; or a master’s degree in a relevant discipline with at least 8 years of relevant analog IC design experience.
• Demonstrated analog IP architecture and hands-on design experience with bandgap references, LDOs, DC–DC regulators, oscillators and PLLs, providing the technical depth to guide implementation and assess feasibility.
• A proven track record of taking several products through the full development lifecycle to mass production, including silicon evaluation, debugging and production support.
• Strong analog circuit fundamentals and practical expertise in transistor-level design, simulation, layout-dependent effects and post-layout verification.
• The ability to translate product and system requirements into robust, reusable analog IP architectures, interface definitions and specifications, with clear reasoning behind key technical trade-offs.
• Experience shaping IP strategy and development roadmaps, engaging product lines to reconcile competing requirements, prioritise capability investments and align near-term delivery with longer-term platform direction.
• Demonstrated experience mentoring junior engineers and providing technical guidance through design reviews.
• Strong communication and presentation skills, with the ability to explain complex technical concepts, present trade-offs and build alignment across engineering teams and product stakeholders.
• A solid understanding of how AI can contribute to analog design and layout, including practical use cases, limitations and the need for independent engineering verification.

Desirable Experience

• Experience in BCD technologies, particularly BCD65, and analog IP development for mixed-signal platforms.
• Experience with supply and voltage monitoring, power-on reset, brownout detection and power or clock sequencing.
• Experience defining reusable IP portfolios, configuration strategies and integration requirements across multiple product families.
• Practical experience with scripting, design-flow automation or evaluation of AI-assisted engineering tools.